Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10791203 | Multi-protocol receiver | Prasad Chalasani, Majid Jalali Far | 2020-09-29 |
| 10742220 | Method and apparatus for operating programmable clock divider using reset paths | Majid Jalali Far | 2020-08-11 |
| 10502769 | Digital voltmeter | William Loh, Prasad Chalasani | 2019-12-10 |
| 10498564 | Receiver for handling high speed transmissions | Majid Jalali Far | 2019-12-03 |
| 10361684 | Duty cycle detection | Majid Jalali Far, Prasad Chalasani, Aram Martirosyan | 2019-07-23 |
| 10094859 | Voltage detector | Prasad Chalasani, Majid Jalali Far | 2018-10-09 |
| 10061340 | Bandgap reference voltage generator | Majid Jalali Far | 2018-08-28 |
| 10014866 | Clock alignment scheme for data macros of DDR PHY | Narasimhan Vasudevan, Prasad Chalasani | 2018-07-03 |
| 9971975 | Optimal data eye for improved Vref margin | Ravindra Kantamani, Prasad Chalasani | 2018-05-15 |
| 9954538 | Clock alignment scheme for data macros of DDR PHY | Narasimhan Vasudevan, Prasad Chalasani | 2018-04-24 |
| 9948310 | Methods and systems for clocking a physical layer interface | Prasad Chalasani | 2018-04-17 |
| 9715907 | Optimal data eye for improved Vref margin | Ravindra Kantamani, Prasad Chalasani | 2017-07-25 |
| 9716492 | Method and circuit for duty cycle detection | — | 2017-07-25 |
| 9564905 | Methods and systems for clocking a physical layer interface | Prasad Chalasani | 2017-02-07 |
| 9467149 | Methods and systems for distributing clock and reset signals across an address macro | Prasad Chalasani | 2016-10-11 |
| 9444463 | Voltage level shifter | — | 2016-09-13 |
| 9349421 | Memory interface | Prasad Chalasani | 2016-05-24 |
| 9337846 | Methods and systems for determining whether a receiver is present on a PCI-express bus | — | 2016-05-10 |
| 9286260 | Serial-to parallel converter using serially-connected stages | — | 2016-03-15 |
| 8952737 | Methods and systems for calibration of a delay locked loop | Kishore Mishra, Purna Mohanty | 2015-02-10 |
| 8669792 | Voltage mode driver using pre-emphasis and de-emphasis signals | — | 2014-03-11 |
| 8643516 | Parallel-to-serial converter | — | 2014-02-04 |
| 6222791 | Slew tolerant clock input buffer and a self-timed memory core thereof | Scott T. Becker | 2001-04-24 |