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Clock alignment scheme for data macros of DDR PHY |
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Clock alignment scheme for data macros of DDR PHY |
Venkata N. S. N. Rao, Prasad Chalasani |
2018-04-24 |
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Receiver architecture for memory reads |
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Stable VCO operation in absence of clock signal |
— |
2012-02-21 |
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Method and apparatus for saving and restoring the state of a power-gated memory device |
— |
2010-12-28 |
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Voltage sensing in a supply regulator for a suspend mode |
— |
2010-06-08 |
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Enhanced voltage regulation with power supply disable capability for low-power operation |
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2010-04-20 |
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Power-on reset circuit for a voltage regulator having multiple power supply voltages |
— |
2010-02-23 |
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Highly reliable and zero static current start-up circuits |
— |
2008-01-22 |
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Bandgap system with tunable temperature coefficient of the output voltage |
— |
2007-12-11 |
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Supply regulator for memory cells with suspend mode capability for low power applications |
— |
2007-09-04 |
| 6509739 |
Method for locating defects and measuring resistance in a test structure |
Martin L. Voogel, Leon Ly Nguyen |
2003-01-21 |