Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8743653 | Reducing dynamic power consumption of a memory circuit | Sridhar Subramanian, Subodh Kumar, Matthew H. Klein | 2014-06-03 |
| 8503264 | Reducing power consumption in a segmented memory | Sridhar Subramanian, Matthew H. Klein, Patrick J. Crotty | 2013-08-06 |
| 8423935 | Method and apparatus for verifying output-based clock gating | Chaiyasit Manovit, Wanlin Cao, Sridhar Subramanian, Alok Kuchlous | 2013-04-16 |
| 8341578 | Clock gater with test features and low setup time | Brian J. Campbell, Shaishav Desai, Edgardo F. Klass, Pradeep Trivedi | 2012-12-25 |
| 8219946 | Method for clock gating circuits | Chaiyasit Manovit, Wanlin Cao, Sridhar Subramanian | 2012-07-10 |
| 8099703 | Method and system for verifying power-optimized electronic designs using equivalency checking | Chaiyasit Manovit, Sridhar Subramanian | 2012-01-17 |
| 7779372 | Clock gater with test features and low setup time | Brian J. Campbell, Shaishav Desai, Edgardo F. Klass, Pradeep Trivedi | 2010-08-17 |
| 7746116 | Method and apparatus to clock-gate a digital integrated circuit by use of feed-forward quiescent input analysis | Chaiyasit Manovit, Sridhar Subramanian, Gerald Gras | 2010-06-29 |
| 7055135 | Method for debugging an integrated circuit | Hong Kim, Amit Majumdar | 2006-05-30 |
| 6658632 | Boundary scan cell architecture with complete set of operational modes for high performance integrated circuits | Ishwardutt Parulkar | 2003-12-02 |
| 6578168 | Method for operating a boundary scan cell design for high performance I/O cells | Ishwardutt Parulkar, Gajendra Prasad Singh, Jaya Prakash Samala | 2003-06-10 |
| 6567944 | Boundary scan cell design for high performance I/O cells | Gajendra Prasad Singh, Jaya Prakash Samala, Ishwardutt Parulkar | 2003-05-20 |
| 6507925 | Spatial and temporal alignment of a scan dump for debug of scan-based designs | Amitava Majumdar, Paul J. Dickinson, Gregory S. Clausen, Cary Chin | 2003-01-14 |
| 6452423 | Circuit for avoiding contention in one-hot or one-cold multiplexer designs | Ashutosh Kumar Das | 2002-09-17 |
| 6081913 | Method for ensuring mutual exclusivity of selected signals during application of test patterns | Marc E. Levitt | 2000-06-27 |
| 5983376 | Automated scan insertion flow for control block design | Yuncheng F. Yu, Arthur M. Lin, Hongyu Li | 1999-11-09 |
| 5898702 | Mutual exclusivity circuit for use in test pattern application scan architecture circuits | Marc E. Levitt | 1999-04-27 |
| 5896396 | Method and apparatus for scan test of SRAM for microprocessors without full scan capability | Amit Sanghani | 1999-04-20 |
| 5881067 | Flip-flop design and technique for scan chain diagnosis | Ashutosh Kumar Das | 1999-03-09 |
| 5774474 | Pipelined scan enable for fast scan testing | Marc E. Levitt | 1998-06-30 |
| 5682391 | Apparatus and method for high speed shifting of test data through an integrated circuit | — | 1997-10-28 |