Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11257560 | Test architecture for die to die interconnect for three dimensional integrated circuits | Sreejit Chakravarty, Fei Su, Puneet Gupta, Wei Ming Lim, Terrence Huat Hin Tan +4 more | 2022-02-22 |
| 10545189 | Granular dynamic test systems and methods | Milind Sonawane, Jonathon E. Colburn, Bala Tarun Nelapatla, Shantanu Sarangi, Rajendra Kumar reddy.S +1 more | 2020-01-28 |
| 10481203 | Granular dynamic test systems and methods | Shantanu Sarangi, Milind Sonawane, Adarsh Kalliat Balagopala | 2019-11-19 |
| 10473720 | Dynamic independent test partition clock | Pavan Kumar Datla Jagannadha, Dheepakkumaran Jayaraman, Anubhav Sinha, Karthikeyan Natarajan, Shantanu Sarangi +2 more | 2019-11-12 |
| 10451676 | Method and system for dynamic standard test access (DSTA) for a logic block reuse | Milind Sonawane, Shantanu Sarangi, Jonathon E. Colburn, Bala Tarun Nelapatla, Sailendra Chadalavda +3 more | 2019-10-22 |
| 10444280 | Independent test partition clock coordination across multiple test partitions | Dheepakkumaran Jayaraman, Karthikeyan Natarajan, Shantanu Sarangi, Milind Sonawane, Sailendra Chadalavda +4 more | 2019-10-15 |
| 10317463 | Scan system interface (SSI) module | Milind Sonawane, Jonathon E. Colburn, Rajendra Kumar reddy.S, Bala Tarun Nelapatla, Sailendra Chadalavda +1 more | 2019-06-11 |
| 10281524 | Test partition external input/output interface control for test partitions in a semiconductor | Sailendra Chadalavda, Shantanu Sarangi, Milind Sonawane, Jonathon E. Colburn, Dan Tobin Smith +2 more | 2019-05-07 |
| 10241148 | Virtual access of input/output (I/O) for test via an on-chip star network | Ashfaq R. Shaikh, Wen-Hung Lo, Punit Kishore, Krishna B. Rajan | 2019-03-26 |
| 9885753 | Scan systems and methods | Farideh Golshan, Venkata Kottapalli, Milind Sonawane, Ketan Kulkarni | 2018-02-06 |
| 9829536 | Performing on-chip partial good die identification | Milind Sonawane, Jonathon E. Colburn | 2017-11-28 |
| 9500706 | Hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support | Sagar Nataraj, Karthikeyan Natarajan, Bo Yang | 2016-11-22 |
| 9395414 | System for reducing peak power during scan shift at the local level for scan based tests | Milind Sonawane, Satya Puvvada | 2016-07-19 |
| 9377510 | System for reducing peak power during scan shift at the global level for scan based tests | Milind Sonawane, Satya Puvvada | 2016-06-28 |
| 9222981 | Global low power capture scheme for cores | Satya Puvvada, Milind Sonawane, Anubhav Sinha, Vishal Agarwal | 2015-12-29 |
| 8943457 | Simulating scan tests with reduced resources | Punit Kishore | 2015-01-27 |
| 8522190 | Power droop reduction via clock-gating for at-speed scan testing | Bo Yang | 2013-08-27 |
| 7305598 | Test clock generation for higher-speed testing of a semiconductor device | Philip Manela | 2007-12-04 |
| 6816991 | Built-in self-testing for double data rate input/output | — | 2004-11-09 |
| 6629277 | LSSD interface | — | 2003-09-30 |
| 6629275 | Reinstate apparatus and method to recreate data background for testing SRAM | Rahesh Y Pendurkar | 2003-09-30 |
| 6477684 | Automatic test pattern generation modeling for LSSD to interface with Muxscan | — | 2002-11-05 |
| 6047386 | Apparatus for scan test of SRAM for microprocessors having full scan capability | Narayanan Sridhar | 2000-04-04 |
| 6014762 | Method and apparatus for scan test of SRAM for microprocessor without full scan capability | Narayanan Sridhar | 2000-01-11 |
| 5923835 | Method for scan test of SRAM for microprocessors having full scan capability | Narayanan Sridhar | 1999-07-13 |