Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9405698 | System and methods for memory expansion | Mario Mazzola, Satyanarayana Nishtala, Luca Cafiero | 2016-08-02 |
| 9026714 | Memory expansion using rank aggregation | Jay Evan Scott Peterson | 2015-05-05 |
| 8825965 | System and methods for memory expansion | Mario Mazzola, Satyanarayana Nishtala, Luca Cafiero | 2014-09-02 |
| 8407394 | System and methods for memory expansion | Mario Mazzola, Satyanarayana Nishtala, Luca Cafiero | 2013-03-26 |
| 7647467 | Tuning DRAM I/O parameters on the fly | Brian D. Hutsell, Sameer M. Gauria, John A. Robinson | 2010-01-12 |
| 7305598 | Test clock generation for higher-speed testing of a semiconductor device | Amit Sanghani | 2007-12-04 |
| 7015740 | Self-adjusting programmable on-chip clock aligner | Eugene M. Feinberg, Richard F. Paul | 2006-03-21 |
| 6035262 | Real time observation serial scan test architecture | Walter E. Gibson, Jeffery A. Sprouse, Eduardo M. Lipiansky, Javad Khakbaz, Michael A. Plum +1 more | 2000-03-07 |
| 6009506 | Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions | Robert L. Jardine, Shannon J. Lynch, Robert W. Horst | 1999-12-28 |
| 5717695 | Output pin for selectively outputting one of a plurality of signals internal to a semiconductor chip according to a programmable register for diagnostics | Peter Birch, John Lin, Daniel R. Ullum | 1998-02-10 |
| 5075844 | Paired instruction processor precise exception handling mechanism | Robert L. Jardine, Shannon J. Lynch, Robert W. Horst | 1991-12-24 |
| 5072364 | Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel | Robert L. Jardine, Shannon J. Lynch, Robert W. Horst | 1991-12-10 |