Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6009506 | Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions | Robert L. Jardine, Philip Manela, Robert W. Horst | 1999-12-28 |
| 5075844 | Paired instruction processor precise exception handling mechanism | Robert L. Jardine, Philip Manela, Robert W. Horst | 1991-12-24 |
| 5072364 | Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel | Robert L. Jardine, Philip Manela, Robert W. Horst | 1991-12-10 |
| 4800486 | Multiple data patch CPU architecture | Robert W. Horst, Cirillo L. Costantino, John M. Beirne | 1989-01-24 |