Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12291219 | Asynchronous in-system testing for autonomous systems and applications | Anitha Kalva, Jae Wu, Shantanu Sarangi, Sailendra Chadalavada, Chen Fang +1 more | 2025-05-06 |
| 11668750 | Performing testing utilizing staggered clocks | Sailendra Chadalavada, Venkat Abilash Reddy Nerallapally, Jaison Daniel Kurien, Bonita Bhaskaran, Shantanu Sarangi +1 more | 2023-06-06 |
| 10890620 | On-chip execution of in-system test utilizing a generalized test image | Shantanu Sarangi, Sailendra Chadalavada, Sumit Raj, Rangavajjula Kameswara Naga Mahesh, Jayesh Kumar Pandey +1 more | 2021-01-12 |
| 10746798 | Field adaptable in-system test mechanisms | Sailendra Chadalavada, Shantanu Sarangi, Sunil Bhavsar, Jue Wu, Bonita Bhaskaran +2 more | 2020-08-18 |
| 10545189 | Granular dynamic test systems and methods | Amit Sanghani, Jonathon E. Colburn, Bala Tarun Nelapatla, Shantanu Sarangi, Rajendra Kumar reddy.S +1 more | 2020-01-28 |
| 10481203 | Granular dynamic test systems and methods | Shantanu Sarangi, Adarsh Kalliat Balagopala, Amit Sanghani | 2019-11-19 |
| 10473720 | Dynamic independent test partition clock | Pavan Kumar Datla Jagannadha, Dheepakkumaran Jayaraman, Anubhav Sinha, Karthikeyan Natarajan, Shantanu Sarangi +2 more | 2019-11-12 |
| 10451676 | Method and system for dynamic standard test access (DSTA) for a logic block reuse | Amit Sanghani, Shantanu Sarangi, Jonathon E. Colburn, Bala Tarun Nelapatla, Sailendra Chadalavda +3 more | 2019-10-22 |
| 10444280 | Independent test partition clock coordination across multiple test partitions | Dheepakkumaran Jayaraman, Karthikeyan Natarajan, Shantanu Sarangi, Amit Sanghani, Sailendra Chadalavda +4 more | 2019-10-15 |
| 10317463 | Scan system interface (SSI) module | Amit Sanghani, Jonathon E. Colburn, Rajendra Kumar reddy.S, Bala Tarun Nelapatla, Sailendra Chadalavda +1 more | 2019-06-11 |
| 10281524 | Test partition external input/output interface control for test partitions in a semiconductor | Sailendra Chadalavda, Shantanu Sarangi, Amit Sanghani, Jonathon E. Colburn, Dan Tobin Smith +2 more | 2019-05-07 |
| 9885753 | Scan systems and methods | Amit Sanghani, Farideh Golshan, Venkata Kottapalli, Ketan Kulkarni | 2018-02-06 |
| 9829536 | Performing on-chip partial good die identification | Jonathon E. Colburn, Amit Sanghani | 2017-11-28 |
| 9395414 | System for reducing peak power during scan shift at the local level for scan based tests | Satya Puvvada, Amit Sanghani | 2016-07-19 |
| 9377510 | System for reducing peak power during scan shift at the global level for scan based tests | Satya Puvvada, Amit Sanghani | 2016-06-28 |
| 9222981 | Global low power capture scheme for cores | Satya Puvvada, Amit Sanghani, Anubhav Sinha, Vishal Agarwal | 2015-12-29 |
| 7334172 | Transition fault detection register with extended shift mode | Michael D. Howard, Jonjen Sern, Vicky Wu | 2008-02-19 |