| 12140632 |
Device under test synchronization with automated test equipment check cycle |
Yongkang Hu, Ramalingam Kolisetti, Abhijeet Samudra |
2024-11-12 |
| 12015411 |
Testable time-to-digital converter |
Emil Gizdarski |
2024-06-18 |
| 11921160 |
Using scan chains to read out data from integrated sensors during scan tests |
Bartosz Gajda |
2024-03-05 |
| 11860751 |
Deterministic data latency in serializer/deserializer-based design for test systems |
Abhijeet Samudra, Ajay Nagarandal, Luis M. Cruz, Milin Kaushik Raijada, Ramalingam Kolisetti +3 more |
2024-01-02 |
| 11662383 |
High-speed functional protocol based test and debug |
Brian Archer, Abhijeet Samudra, Kranthi Kandula, Amit Kapatkar, Akshay Gupta +2 more |
2023-05-30 |
| 11626178 |
Packetized power-on-self-test controller for built-in self-test |
Ramalingam Kolisetti, Amit Purohit, Sai Manish Rao Marru, Sahil Soni, Salvatore Talluto |
2023-04-11 |
| 11257560 |
Test architecture for die to die interconnect for three dimensional integrated circuits |
Sreejit Chakravarty, Fei Su, Puneet Gupta, Wei Ming Lim, Terrence Huat Hin Tan +4 more |
2022-02-22 |
| 10995361 |
Multiplexed signal amplified FISH via splinted ligation amplification and sequencing |
Fei Chen, Asmamaw Wassie, Shahar Alon, Adam Marblestone, Andrew Payne +1 more |
2021-05-04 |
| 10473720 |
Dynamic independent test partition clock |
Pavan Kumar Datla Jagannadha, Dheepakkumaran Jayaraman, Karthikeyan Natarajan, Shantanu Sarangi, Amit Sanghani +2 more |
2019-11-12 |
| 9222981 |
Global low power capture scheme for cores |
Satya Puvvada, Milind Sonawane, Amit Sanghani, Vishal Agarwal |
2015-12-29 |
