Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date | Approx Value ⓘ |
|---|---|---|---|---|
| 11257560 | Test architecture for die to die interconnect for three dimensional integrated circuits | Sreejit Chakravarty, Fei Su, Puneet Gupta, Terrence Huat Hin Tan, Amit Sanghani +4 more | 2022-02-22 | $16,582,000 |
| 11140018 | Method and apparatus for intra-symbol multi-dimensional modulation | Arthur Lee, Francis Chukwuemeka Onochie, Sina Rafati, Jeffrey Stuart Koonce, Michael Tembeck +2 more | 2021-10-05 | |
| 10236076 | Methods and apparatus for predictable protocol aware testing on memory interface | Madhu Rao, Alvin Shing Chye Goh, Kim Leong Lee, Terrence Huat Hin Tan, Vui Yong Liew +1 more | 2019-03-19 | $29,538,000 |