Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12352811 | Validating test patterns ported between different levels of a hierarchical design of an integrated circuit | Andrea Costa, Frederic J. Neuveux, Sorin Ioan Popa, Leela Krishna Thota | 2025-07-08 |
| 11626178 | Packetized power-on-self-test controller for built-in self-test | Anubhav Sinha, Ramalingam Kolisetti, Amit Purohit, Sai Manish Rao Marru, Sahil Soni | 2023-04-11 |
| 11237210 | Layout-aware test pattern generation and fault detection | Alodeep Sanyal, Girish A. Patankar, Rohit Kapur | 2022-02-01 |
| 11132484 | Controlling clocks and resets in a logic built in self-test | Frederic J. Neuveux | 2021-09-28 |
| 10254343 | Layout-aware test pattern generation and fault detection | Alodeep Sanyal, Girish A. Patankar, Rohit Kapur | 2019-04-09 |