Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12352811 | Validating test patterns ported between different levels of a hierarchical design of an integrated circuit | Andrea Costa, Frederic J. Neuveux, Salvatore Talluto, Leela Krishna Thota | 2025-07-08 |
| 11694010 | Reformatting scan patterns in presence of hold type pipelines | Amit Purohit, Denis Martin, Paras Chhabra | 2023-07-04 |
| 11036907 | Automatic testbench generator for test-pattern validation | Slimane Boutobza, Andrea Costa | 2021-06-15 |