Issued Patents All Time
Showing 26–44 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5802340 | Method and system of executing speculative store instructions in a parallel processing computer system | Rajesh Patel | 1998-09-01 |
| 5802386 | Latency-based scheduling of instructions in a superscalar processor | James Allan Kahle, Robert G. McDonald | 1998-09-01 |
| 5802556 | Method and apparatus for correcting misaligned instruction data | Rajesh Patel | 1998-09-01 |
| 5787479 | Method and system for preventing information corruption in a cache memory caused by an occurrence of a bus error during a linefill operation | Romesh Mangho Jessani, Belliappa Kuttanna, Rajesh Patel | 1998-07-28 |
| 5765215 | Method and system for efficient rename buffer deallocation within a processor | Muhammad Afsar, Rajesh B. Patel | 1998-06-09 |
| 5764940 | Processor and method for executing a branch instruction and an associated target instruction utilizing a single instruction fetch | Rajesh Patel, Romesh Mangho Jessani | 1998-06-09 |
| 5764969 | Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization | James Allan Kahle, Albert J. Loper, Aubrey Deene Ogden, John V. Sell | 1998-06-09 |
| 5765191 | Method for implementing a four-way least recently used (LRU) mechanism in high-performance | Albert J. Loper, Rajesh Patel, Michael Putrino | 1998-06-09 |
| 5758141 | Method and system for selective support of non-architected instructions within a superscaler processor system utilizing a special access bit within a machine state register | James Allan Kahle, Albert J. Loper, Aubrey Deene Ogden, John V. Sell | 1998-05-26 |
| 5758140 | Method and system for emulating instructions by performing an operation directly using special-purpose register contents | James Allan Kahle | 1998-05-26 |
| 5758117 | Method and system for efficiently utilizing rename buffers to reduce dispatch unit stalls in a superscalar processor | Rajesh Patel | 1998-05-26 |
| 5754811 | Instruction dispatch queue for improved instruction cache to queue timing | Michael Putrino, Albert J. Loper | 1998-05-19 |
| 5752014 | Automatic selection of branch prediction methodology for subsequent branch instruction based on outcome of previous branch prediction | Albert J. Loper | 1998-05-12 |
| 5732235 | Method and system for minimizing the number of cycles required to execute semantic routines | James Allan Kahle, Larry B. Phillips, Russell A. Reininger | 1998-03-24 |
| 5717587 | Method and system for recording noneffective instructions within a data processing system | Bryan Black, Marvin Denman, Lee Evan Eisen, Robert T. Golla, Albert J. Loper +1 more | 1998-02-10 |
| 5694565 | Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions | James Allan Kahle, Albert J. Loper, Aubrey Deene Ogden | 1997-12-02 |
| 5664120 | Method for executing instructions and execution unit instruction reservation table within an in-order completion processor | Muhammad Afsar | 1997-09-02 |
| 5619408 | Method and system for recoding noneffective instructions within a data processing system | Bryan Black, Marvin Denman, Lee Evan Eisen, Robert T. Golla, Albert J. Loper +1 more | 1997-04-08 |
| 5611063 | Method for executing speculative load instructions in high-performance processors | Albert J. Loper, Michael Putrino | 1997-03-11 |