Issued Patents All Time
Showing 1–25 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11404532 | Fingered capacitor with low-k and ultra-low-k dielectric layers | Chunshan Yin, Yu-Hsien Chen | 2022-08-02 |
| 10770539 | Fingered capacitor with low-K and ultra-low-K dielectric layers | Chunshan Yin, Yu-Hsien Chen | 2020-09-08 |
| 10680087 | Gated diode having fingers with elevated gates | Chunshan Yin, Yu-Hsien Chen | 2020-06-09 |
| 10153349 | Methods and structures for a split gate memory cell structure | Sung-Taeg Kang | 2018-12-11 |
| 10026820 | Split gate device with doped region and method therefor | Weize Chen, Konstantin V. Loiko, Jane A. Yater | 2018-07-17 |
| 9847397 | Method of forming split gate memory with improved reliability | Konstantin V. Loiko, Jane A. Yater | 2017-12-19 |
| 9685339 | Scalable split gate memory cell array | Jane A. Yater, Sung-Taeg Kang, Ronald J. Syzdek | 2017-06-20 |
| 9653164 | Method for integrating non-volatile memory cells with static random access memory cells and logic transistors | Laureen H. Parker | 2017-05-16 |
| 9590058 | Methods and structures for a split gate memory cell structure | Sung-Taeg Kang | 2017-03-07 |
| 9559178 | Non-volatile memory (NVM) cell and device structure integration | Satoshi Sekine | 2017-01-31 |
| 9548314 | Method of making a non-volatile memory (NVM) with trap-up reduction | Konstantin V. Loiko, Juanyi Yin | 2017-01-17 |
| 9514945 | Nanocrystal memory and methods for forming same | Euhngi Lee | 2016-12-06 |
| 9437500 | Method of forming supra low threshold devices | — | 2016-09-06 |
| 9397201 | Non-volatile memory (NVM) cell and a method of making | Jacob T. Williams, Sung-Taeg Kang, David G. Kolar, Jane A. Yater | 2016-07-19 |
| 9397176 | Method of forming split gate memory with improved reliability | Konstantin V. Loiko, Jane A. Yater | 2016-07-19 |
| 9368499 | Method of forming different voltage devices with high-k metal gate | Asanga H. Perera, Sung-Taeg Kang | 2016-06-14 |
| 9349453 | Semiconductor memory cell and driver circuitry with gate oxide formed simultaneously | Tahmina Akhter, Gilles J. Muller | 2016-05-24 |
| 9331092 | Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays | Jane A. Yater, Sung-Taeg Kang | 2016-05-03 |
| 9275864 | Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates | Asanga H. Perera, Sung-Taeg Kang, Jane A. Yater | 2016-03-01 |
| 9252246 | Integrated split gate non-volatile memory cell and logic device | Asanga H. Perera, Sung-Taeg Kang, Jane A. Yater | 2016-02-02 |
| 9219167 | Non-volatile memory (NVM) cell | Jacob T. Williams, Sung-Taeg Kang, David G. Kolar, Jane A. Yater | 2015-12-22 |
| 9165652 | Split-gate memory cells having select-gate sidewall metal silicide regions and related manufacturing methods | Sung-Taeg Kang | 2015-10-20 |
| 9142566 | Method of forming different voltage devices with high-K metal gate | Asanga H. Perera, Sung-Taeg Kang | 2015-09-22 |
| 9129855 | Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology | Asanga H. Perera, Sung-Taeg Kang, Jane A. Yater | 2015-09-08 |
| 9129996 | Non-volatile memory (NVM) cell and high-K and metal gate transistor integration | Frank K. Baker, Jr. | 2015-09-08 |