Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12363936 | Nanosheet transistors with reduced source/drain resistance and associated method of manufacture | Mark D. Hall, Craig A. Cavins, Tushar P. Merchant | 2025-07-15 |
| 9728410 | Split-gate non-volatile memory (NVM) cell and method therefor | Craig T. Swift | 2017-08-08 |
| 9368499 | Method of forming different voltage devices with high-k metal gate | Cheong Min Hong, Sung-Taeg Kang | 2016-06-14 |
| 9318568 | Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor | Sung-Taeg Kang | 2016-04-19 |
| 9275864 | Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates | Sung-Taeg Kang, Jane A. Yater, Cheong Min Hong | 2016-03-01 |
| 9252246 | Integrated split gate non-volatile memory cell and logic device | Cheong Min Hong, Sung-Taeg Kang, Jane A. Yater | 2016-02-02 |
| 9142566 | Method of forming different voltage devices with high-K metal gate | Cheong Min Hong, Sung-Taeg Kang | 2015-09-22 |
| 9136129 | Non-volatile memory (NVM) and high-k and metal gate integration using gate-last methodology | — | 2015-09-15 |
| 9136360 | Methods and structures for charge storage isolation in split-gate memory arrays | Ko-Min Chang, Craig T. Swift | 2015-09-15 |
| 9129855 | Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology | Cheong Min Hong, Sung-Taeg Kang, Jane A. Yater | 2015-09-08 |
| 9105748 | Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor | Craig T. Swift | 2015-08-11 |
| 9082837 | Nonvolatile memory bitcell with inlaid high k metal select gate | — | 2015-07-14 |
| 9082650 | Integrated split gate non-volatile memory cell and logic structure | Cheong Min Hong, Sung-Taeg Kang, Byoung W. Min, Jane A. Yater | 2015-07-14 |
| 8969940 | Method of gate strapping in split-gate memory cell with inlaid gate | Jane A. Yater, Cheong Min Hong, Sung-Taeg Kang | 2015-03-03 |
| 8901632 | Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology | Cheong Min Hong, Sung-Taeg Kang, Byoung W. Min, Jane A. Yater | 2014-12-02 |
| 8877585 | Non-volatile memory (NVM) cell, high voltage transistor, and high-K and metal gate transistor integration | Cheong Min Hong, Sung-Taeg Kang | 2014-11-04 |
| 8871598 | Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology | — | 2014-10-28 |
| 6524931 | Method for forming a trench isolation structure in an integrated circuit | — | 2003-02-25 |
| 6362057 | Method for forming a semiconductor device | William J. Taylor, Jr., Suresh Venkatesan | 2002-03-26 |
| 5786263 | Method for forming a trench isolation structure in an integrated circuit | — | 1998-07-28 |
| 5698893 | Static-random-access memory cell with trench transistor and enhanced stability | J. David Burnett | 1997-12-16 |
| 5665202 | Multi-step planarization process using polishing at two different pad pressures | Chitra Subramanian, James D. Hayden, Subramoney Iyer | 1997-09-09 |