Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8766362 | Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner | Konstantin V. Loiko, Rode R. Mora, Michael D. Turner, Brian A. Winstead, Mark D. Hall | 2014-07-01 |
| 8236638 | Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner | Konstantin V. Loiko, Rode R. Mora, Michael D. Turner, Brian A. Winstead, Mark D. Hall | 2012-08-07 |
| 7687370 | Method of forming a semiconductor isolation trench | John J. Hackenberg, Rode R. Mora, Suresh Venkatesan | 2010-03-30 |
| 7670895 | Process of forming an electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer | Peter J. Beckage, Mohamad Jahanbani, Michael D. Turner | 2010-03-02 |
| 7528078 | Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer | Kuang-Hsin Chen, Laegu Kang, Rode R. Mora, Michael D. Turner | 2009-05-05 |
| 7491622 | Process of forming an electronic device including a layer formed using an inductively coupled plasma | Michael D. Turner, Mohamad Jahanbani, Mark D. Hall | 2009-02-17 |
| 7037857 | Method for elimination of excessive field oxide recess for thin Si SOI | Mark D. Hall, Mohamad Jahanbani, Michael D. Turner | 2006-05-02 |
| 6979627 | Isolation trench | Choh Fei Yeap, Yongjoo Jeon, Michael D. Turner | 2005-12-27 |