LK

Laegu Kang

Globalfoundries: 8 patents #444 of 4,424Top 15%
FS Freeescale Semiconductor: 8 patents #392 of 3,767Top 15%
IBM: 2 patents #32,839 of 70,183Top 50%
Samsung: 2 patents #37,631 of 75,807Top 50%
Motorola: 2 patents #4,475 of 12,470Top 40%
Infineon Technologies Ag: 1 patents #168 of 446Top 40%
GP Globalfoundries Singapore Pte.: 1 patents #427 of 828Top 55%
CM Chartered Semiconductor Manufacturing: 1 patents #419 of 840Top 50%
Overall (All Time): #239,260 of 4,157,543Top 6%
19
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10483172 Transistor device structures with retrograde wells in CMOS applications Vara Govindeswara Reddy Vakada, Michael Ganz, Yi Qi, Puneet Khanna, Srikanth B. Samavedam +2 more 2019-11-19
9852954 Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures Vara Govindeswara Reddy Vakada, Michael Ganz, Yi Qi, Puneet Khanna, Srikanth B. Samavedam +2 more 2017-12-26
9362357 Blanket EPI super steep retrograde well formation without Si recess Vara Govindeswara Reddy Vakada, Michael Ganz, Yi Qi, Puneet Khanna, Sri Charan Vemula +1 more 2016-06-07
9209181 Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures Vara Govindeswara Reddy Vakada, Michael Ganz, Yi Qi, Puneet Khanna, Srikanth B. Samavedam +2 more 2015-12-08
9099380 Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device Vara Govindeswara Reddy Vakada, Michael Ganz, Yi Qi, Puneet Khanna, Sri Charan Vemula +1 more 2015-08-04
9099525 Blanket EPI super steep retrograde well formation without Si recess Vara Govindeswara Reddy Vakada, Michael Ganz, Yi Qi, Puneet Khanna, Sri Charan Vemula +1 more 2015-08-04
8916442 Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device Vara Govindeswara Reddy Vakada, Michael Ganz, Yi Qi, Puneet Khanna, Sri Charan Vemula +1 more 2014-12-23
8809178 Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents Yanxiang Liu, Michael Hargrove, Xiaodong Yang, Hans Van Meer, Christian Gruensfelder +1 more 2014-08-19
8790972 Methods of forming CMOS transistors using tensile stress layers and hydrogen plasma treatment Yong-Kuk Jeong, Kim Nam Sung, Dae Won Yang 2014-07-29
8445969 High pressure deuterium treatment for semiconductor/high-K insulator interface Xiangdong Chen, Weipeng Li, Dae-Gyu Park, Melanie J. Sherony 2013-05-21
8106462 Balancing NFET and PFET performance using straining layers Xiangdong Chen, Weipeng Li, Anda C. Mocuta, Dae-Gyu Park, Melanie J. Sherony +8 more 2012-01-31
7795089 Forming a semiconductor device having epitaxially grown source and drain regions Vishal P. Trivedi, Da Zhang 2010-09-14
7528078 Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer Toni D. Van Gompel, Kuang-Hsin Chen, Rode R. Mora, Michael D. Turner 2009-05-05
7517742 Area diode formation in SOI application Byoung W. Min, Michael G. Khazhinsky 2009-04-14
7186596 Vertical diode formation in SOI application Byoung W. Min, Michael G. Khazhinsky 2007-03-06
7126172 Integration of multiple gate dielectrics by surface protection Sangwoo Lim, Geoffrey Yeap 2006-10-24
6724048 Body-tied silicon on insulator semiconductor device and method therefor Byoung W. Min, Michael A. Mendicino 2004-04-20
6620656 Method of forming body-tied silicon on insulator semiconductor device Byoung W. Min, Michael A. Mendicino 2003-09-16
5068200 Method of manufacturing DRAM cell Kyungtae Kim 1991-11-26