Issued Patents All Time
Showing 25 most recent of 89 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12426226 | Macro and SRAM bit cell cooptimizatoin for performance (long/shortwordline combo SRAM) | Ping-Wei Wang, Lien Jung Hung, Kuo-Hsiu Hsu, Kian-Long Lim, Yu-Kuan Lin +3 more | 2025-09-23 |
| 12363937 | Multi-gate device and related methods | Tsung-Lin Lee, Da-Wen Lin, Chih Chieh Yeh | 2025-07-15 |
| 12356664 | Device and method of fabricating multigate devices having different channel configurations | Tsung-Lin Lee, Da-Wen Lin, Chih-hung Yeh | 2025-07-08 |
| 12255230 | Semiconductor structure and method for forming the same | Tsung-Lin Lee, Da-Wen Lin, Chih Chieh Yeh | 2025-03-18 |
| 12040383 | Multi-gate device and related methods | Tsung-Lin Lee, Da-Wen Lin, Chih Chieh Yeh | 2024-07-16 |
| 12027202 | SRAM structures | Ping-Wei Wang, Chia-Hao Pao, Yu-Kuan Lin, Kian-Long Lim | 2024-07-02 |
| 12016169 | Optimized static random access memory | Ping-Wei Wang, Lien Jung Hung, Kuo-Hsiu Hsu, Kian-Long Lim, Yu-Kuan Lin +3 more | 2024-06-18 |
| 11777016 | Method of forming backside power rails | Ping-Wei Wang, Chih-Chuan Yang, Yu-Kuan Lin | 2023-10-03 |
| 11475942 | SRAM structures | Ping-Wei Wang, Chia-Hao Pao, Yu-Kuan Lin, Kian-Long Lim | 2022-10-18 |
| 11411100 | Method of forming backside power rails | Ping-Wei Wang, Chih-Chuan Yang, Yu-Kuan Lin | 2022-08-09 |
| 11393831 | Optimized static random access memory | Ping-Wei Wang, Lien Jung Hung, Kuo-Hsiu Hsu, Kian-Long Lim, Yu-Kuan Lin +3 more | 2022-07-19 |
| 10559501 | Self-aligned quadruple patterning process for Fin pitch below 20nm | Stanley Seungchul Song, Jeffrey Junhao Xu, Da Yang, Kern Rim | 2020-02-11 |
| 10497625 | Method and apparatus of multi threshold voltage CMOS | Jeffrey Junhao Xu | 2019-12-03 |
| 10439039 | Integrated circuits including a FinFET and a nanostructure FET | Stanley Seungchul Song, Jeffrey Junhao Xu, Kern Rim | 2019-10-08 |
| 10354912 | Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs) | Jeffrey Junhao Xu, John Jianhong Zhu | 2019-07-16 |
| 10163792 | Semiconductor device having an airgap defined at least partially by a protective structure | John Jianhong Zhu, Jeffrey Junhao Xu, Stanley Seungchul Song, Kern Rim | 2018-12-25 |
| 10157992 | Nanowire device with reduced parasitics | Mustafa Badaroglu, Vladimir Machkaoutsan, Stanley Seungchul Song, Jeffrey Junhao Xu, Matthew Michael Nowak | 2018-12-18 |
| 10141317 | Metal layers for a three-port bit cell | Niladri Narayan Mojumder, Ritu Chaba, Ping-Lin Liu, Stanley Seungchul Song, Zhongze Wang | 2018-11-27 |
| 10079293 | Semiconductor device having a gap defined therein | Jeffrey Junhao Xu, Kern Rim, John Jianhong Zhu, Stanley Seungchul Song, Mustafa Badaroglu +2 more | 2018-09-18 |
| 10043796 | Vertically stacked nanowire field effect transistors | Vladimir Machkaoutsan, Stanley Seungchul Song, Mustafa Badaroglu, John Jianhong Zhu, Junjing Bao +3 more | 2018-08-07 |
| 10037795 | Seven-transistor static random-access memory bitcell with reduced read disturbance | Seong-Ook Jung, Younghwi Yang, Stanley Seungchul Song, Zhongze Wang | 2018-07-31 |
| 10032678 | Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices | Jeffrey Junhao Xu, Stanley Seungchul Song, Da Yang, Vladimir Machkaoutsan, Mustafa Badaroglu | 2018-07-24 |
| 9984029 | Variable interconnect pitch for improved performance | Kern Rim, Stanley Seungchul Song, Xiangdong Chen, Raymond George Stephany, John Jianhong Zhu +2 more | 2018-05-29 |
| 9953979 | Contact wrap around structure | Jeffrey Junhao Xu, Stanley Seungchul Song, Vladimir Machkaoutsan, Mustafa Badaroglu, Junjing Bao +2 more | 2018-04-24 |
| 9941156 | Systems and methods to reduce parasitic capacitance | Shiqun Gu, Vidhya Ramachandran, Christine Hau-Riege, John Jianhong Zhu, Jeffrey Junhao Xu +2 more | 2018-04-10 |