Issued Patents All Time
Showing 1–25 of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12426226 | Macro and SRAM bit cell cooptimizatoin for performance (long/shortwordline combo SRAM) | Ping-Wei Wang, Lien Jung Hung, Kuo-Hsiu Hsu, Kian-Long Lim, Yu-Kuan Lin +3 more | 2025-09-23 |
| 12419197 | Memory device and method of forming the same | Hsin-Wen Su, Jui-Lin Chen, Shih-Hao Lin, Ming-Yen Chuang, Chenchen Jacob Wang +1 more | 2025-09-16 |
| 12408427 | Crown bulk for FinFET device | Yu-Kuan Lin | 2025-09-02 |
| 12374590 | Test structure and test method thereof | Jing-Yi Lin, Kuo-Hsiu Hsu, Lien Jung Hung | 2025-07-29 |
| 12367925 | Static random access memory layout | Jui Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu, Lien Jung Hung +1 more | 2025-07-22 |
| 12367924 | SRAM design with four-poly-pitch | Feng-Ming Chang, Kuo-Hsiu Hsu, Ping-Wei Wang | 2025-07-22 |
| 12363959 | Semiconductor device and method | Shih-Hao Lin | 2025-07-15 |
| 12356660 | Multi-gate device and related methods | Shih-Hao Lin, Chih-Hsuan Chen, Bwo-Ning Chen, Cha-Hon Chou, Hsin-Wen Su +1 more | 2025-07-08 |
| 12349330 | Shared pick-up regions for memory devices | Chao-Yuan Chang, Shih-Hao Lin, Chia-Hao Pao, Feng-Ming Chang, Lien Jung Hung +1 more | 2025-07-01 |
| 12349329 | Memory device and method for forming the same | Hsin-Wen Su, Shih-Hao Lin, Yu-Kuan Lin, Lien Jung Hung, Ping-Wei Wang | 2025-07-01 |
| 12302604 | Multi-gate device and related methods | Shih-Hao Lin, Chong-De Lien, Chih-Yu Hsu, Ming-Shuan Li, Hsin-Wen Su | 2025-05-13 |
| 12294030 | Nano-sheet-based complementary metal-oxide-semiconductor devices with asymmetric inner spacers | Shih-Hao Lin, Chih-Hsuan Chen, Chia-Hao Pao, Chih-Yu Hsu, Hsin-Wen Su +1 more | 2025-05-06 |
| 12274045 | Well pick-up region design for improving memory macro performance | Chang-Ta Yang, Ping-Wei Wang | 2025-04-08 |
| 12256529 | Memory device and method for forming thereof | — | 2025-03-18 |
| 12249636 | Tuning gate lengths in multi-gate field effect transistors | Chia-Hao Pao, Shih-Hao Lin, Kian-Long Lim, Chih-Hsuan Chen, Ping-Wei Wang | 2025-03-11 |
| 12243912 | Source/drain feature for multigate device performance and method of fabricating thereof | Wen-Chun Keng, Chong-De Lien, Shih-Hao Lin, Hsin-Wen Su, Ping-Wei Wang | 2025-03-04 |
| 12219747 | Memory active region layout for improving memory performance | Chia-Hao Pao, Shih-Hao Lin, Chih-Hsuan Chen, Kian-Long Lim, Chao-Yuan Chang +3 more | 2025-02-04 |
| 12211944 | Semiconductor device with fish bone structure and methods of forming the same | Kuo-Hsiu Hsu | 2025-01-28 |
| 12213297 | Semiconductor devices with threshold voltage modulation layer | Shih-Hao Lin, Chih-Hsiang Huang, Shang-Rong Li, Jui-Lin Chen, Ming-Shuan Li | 2025-01-28 |
| 12200921 | Memory device and method for forming the same | Hsin-Wen Su, Shih-Hao Lin, Yu-Kuan Lin, Lien Jung Hung, Ping-Wei Wang | 2025-01-14 |
| 12191306 | Integrated circuit with latch-up immunity | Jing-Yi Lin, Shih-Hao Lin | 2025-01-07 |
| 12178032 | Source/drain feature separation structure | Wen-Chun Keng, Kuo-Hsiu Hsu, Lien Jung Hung, Ping-Wei Wang | 2024-12-24 |
| 12160985 | Shared bit lines for memory cells | Ping-Wei Wang, Lien Jung Hung, Feng-Ming Chang, Kuo-Hsiu Hsu, Kian-Long Lim +1 more | 2024-12-03 |
| 12142684 | Cut metal gate in memory macro edge and middle strap | Hsin-Wen Su, Yu-Kuan Lin, Chang-Ta Yang, Shih-Hao Lin | 2024-11-12 |
| 12101921 | SRAM speed and margin optimization via spacer tuning | Shih-Hao Lin, Hsin-Wen Su, Kian-Long Lim, Chien-Chih Lin | 2024-09-24 |