Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11508725 | Layout construction for addressing electromigration | Seid Hadi Rasouli, Michael Brunolli, Mickael Malabry, Sucheta Kumar Harish, Prathiba Balasubramanian +4 more | 2022-11-22 |
| 10600785 | Layout construction for addressing electromigration | Seid Hadi Rasouli, Michael Brunolli, Mickael Malabry, Sucheta Kumar Harish, Prathiba Balasubramanian +4 more | 2020-03-24 |
| 9972624 | Layout construction for addressing electromigration | Seid Hadi Rasouli, Michael Brunolli, Mickael Malabry, Sucheta Kumar Harish, Prathiba Balasubramanian +4 more | 2018-05-15 |
| 9941156 | Systems and methods to reduce parasitic capacitance | Shiqun Gu, Vidhya Ramachandran, John Jianhong Zhu, Jeffrey Junhao Xu, Jihong Choi +2 more | 2018-04-10 |
| 9171782 | Stacked redistribution layers on die | You-Wen Yau, Kevin Patrick Caffey, Lizabeth Keser, Gene H. McAllister, Reynante Tamunan Alvarado +2 more | 2015-10-27 |
| 8723321 | Copper interconnects with improved electromigration lifetime | Christy Mei-Chu Woo, Jun Zhai, Paul R. Besser, Kok Yong Yiang, Richard C. Blish, II | 2014-05-13 |
| 8482125 | Conductive sidewall for microbumps | Arvind Chandrasekaran, Shiqun Gu | 2013-07-09 |
| 7818655 | Method for quantitative detection of multiple electromigration failure modes | Eun Joo Lee | 2010-10-19 |
| 7451411 | Integrated circuit design system | Amit P. Marathe | 2008-11-11 |
| 7153774 | Method of making a semiconductor device that has copper damascene interconnects with enhanced electromigration reliability | Stefan Hau-Riege, Wen-Yue Zheng | 2006-12-26 |
| 7135775 | Enhancement of an interconnect | Stephen Chambers, Valery M. Dubin, Andrew Ott | 2006-11-14 |
| 7026225 | Semiconductor component and method for precluding stress-induced void formation in the semiconductor component | Amit P. Marathe, John Sanchez | 2006-04-11 |
| 6897476 | Test structure for determining electromigration and interlayer dielectric failure | Hyeon-Seag Kim, Seung-Hyun Rhee, Amit P. Marathe | 2005-05-24 |
| 6870262 | Wafer-bonding using solder and method of making the same | Stefan Hau-Riege | 2005-03-22 |
| 6867056 | System and method for current-enhanced stress-migration testing of interconnect | Amit P. Marathe | 2005-03-15 |
| 6822473 | Determination of permeability of layer material within interconnect | Stefan Hau-Riege, Amit P. Marathe | 2004-11-23 |
| 6822437 | Interconnect test structure with slotted feeder lines to prevent stress-induced voids | John Sanchez, Amit P. Marathe | 2004-11-23 |
| 6818557 | Method of forming SiC capped copper interconnects with reduced hillock formation and improved electromigration resistance | Minh Van Ngo, Steve Avanzino, Robert A. Huertas | 2004-11-16 |
| 6768323 | System and method for determining location of extrusion in interconnect | Stefan Hau-Riege | 2004-07-27 |
| 6762597 | Structure, system, and method for assessing electromigration permeability of layer material within interconnect | Stefan Hau-Riege, Amit P. Marathe | 2004-07-13 |
| 6725433 | Method for assessing the reliability of interconnects | Amit P. Marathe | 2004-04-20 |
| 6714037 | Methodology for an assessment of the degree of barrier permeability at via bottom during electromigration using dissimilar barrier thickness | Amit P. Marathe | 2004-03-30 |
| 6667225 | Wafer-bonding using solder and method of making the same | Stefan Hau-Riege | 2003-12-23 |
| 6518184 | Enhancement of an interconnect | Stephen Chambers, Valery M. Dubin, Andrew Ott | 2003-02-11 |