Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7155359 | Determination of device failure characteristic | Amit P. Marathe, Kurt Taylor | 2006-12-26 |
| 6929963 | Semiconductor component and method of manufacture and monitoring | — | 2005-08-16 |
| 6909293 | Space-saving test structures having improved capabilities | — | 2005-06-21 |
| 6897476 | Test structure for determining electromigration and interlayer dielectric failure | Seung-Hyun Rhee, Christine Hau-Riege, Amit P. Marathe | 2005-05-24 |
| 6873932 | Method and apparatus for predicting semiconductor device lifetime | — | 2005-03-29 |
| 6861696 | Structure and method for a two-bit memory cell | Nian Yang, Munseork Choi | 2005-03-01 |
| 6856160 | Maximum VCC calculation method for hot carrier qualification | Amit P. Marathe, Nian Yang, Tien-Chun Yang | 2005-02-15 |
| 6831451 | Method for adjusting a Weibull slope for variations in temperature and bias voltage | Jongwook Kye | 2004-12-14 |
| 6825684 | Hot carrier oxide qualification method | Amit P. Marathe, Nian Yang, Tien-Chun Yang | 2004-11-30 |
| 6812514 | High density floating gate flash memory and fabrication processes therefor | Nian Yang, Zhigang Wang | 2004-11-02 |
| 6806696 | Method for determining a Weibull slope having a bias voltage variation adjustment | — | 2004-10-19 |
| 6784061 | Process to improve the Vss line formation for high density flash memory and related structure associated therewith | Nian Yang, John Jianshi Wang | 2004-08-31 |
| 6784682 | Method of detecting shallow trench isolation corner thinning by electrical trapping | Tien-Chun Yang, Nian Yang | 2004-08-31 |
| 6762463 | MOSFET with SiGe source/drain regions and epitaxial gate dielectric | — | 2004-07-13 |
| 6737876 | Method and system for determining an operating voltage using a source/drain to gate overlap induced scaling factor | — | 2004-05-18 |
| 6734028 | Method of detecting shallow trench isolation corner thinning by electrical stress | Tien-Chun Yang, Nian Yang | 2004-05-11 |
| 6693009 | Flash memory cell with minimized floating gate to drain/source overlap for minimizing charge leakage | Unsoon Kim, Munseork Choi | 2004-02-17 |
| 6660588 | High density floating gate flash memory and fabrication processes therefor | Nian Yang, Zhigang Wang | 2003-12-09 |
| 6646326 | Method and system for providing source/drain-gate spatial overlap engineering for low-power devices | Jongwook Kye | 2003-11-11 |
| 6642106 | Method for increasing core gain in flash memory device using strained silicon | Nian Yang, Zhigang Wang | 2003-11-04 |
| 6624488 | Epitaxial silicon growth and usage of epitaxial gate insulator for low power, high performance devices | — | 2003-09-23 |
| 6621114 | MOS transistors with high-k dielectric gate insulator for reducing remote scattering | Joong S. Jeon | 2003-09-16 |
| 6617179 | Method and system for qualifying an ONO layer in a semiconductor device | — | 2003-09-09 |
| 6534363 | High voltage oxidation method for highly reliable flash memory devices | — | 2003-03-18 |
| 6514822 | Method and system for reducing thinning of field isolation structures in a flash memory device | — | 2003-02-04 |