Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12374625 | Microelectronic assemblies having topside power delivery structures | Bernd Waidhas, Carlton Hanna, Stephen L. Morein, Georg Seidemann | 2025-07-29 |
| 12362251 | Fan out package with integrated peripheral devices and methods | Bernd Waidhas, Thomas Ort, Thomas Wagner | 2025-07-15 |
| 12243828 | Microelectronic assemblies having topside power delivery structures | Bernd Waidhas, Carlton Hanna, Stephen L. Morein, Georg Seidemann | 2025-03-04 |
| 12211796 | Microelectronic assemblies having topside power delivery structures | Bernd Waidhas, Carlton Hanna, Stephen L. Morein, Georg Seidemann | 2025-01-28 |
| 12057364 | Package formation methods including coupling a molded routing layer to an integrated routing layer | Thomas Ort, Thomas Wagner, Bernd Waidhas | 2024-08-06 |
| 11955395 | Fan out package with integrated peripheral devices and methods | Bernd Waidhas, Thomas Ort, Thomas Wagner | 2024-04-09 |
| 11581287 | Chip scale thin 3D die stacked package | Robert L. Sankman, Sanka Ganesan, Bernd Waidhas, Thomas Wagner | 2023-02-14 |
| 11508637 | Fan out package and methods | Thomas Ort, Thomas Wagner, Bernd Waidhas | 2022-11-22 |
| 11404339 | Fan out package with integrated peripheral devices and methods | Bernd Waidhas, Thomas Ort, Thomas Wagner | 2022-08-02 |
| 11211337 | Face-up fan-out electronic package with passive components using a support | Thomas Ort, Thomas Wagner, Bernd Waidhas | 2021-12-28 |
| 10720393 | Molded substrate package in fan-out wafer level package | Thomas Ort, Thomas Wagner, Bernd Waidhas | 2020-07-21 |
| 10699980 | Fan out package with integrated peripheral devices and methods | Bernd Waidhas, Thomas Ort, Thomas Wagner | 2020-06-30 |
| 10665522 | Package including an integrated routing layer and a molded routing layer | Thomas Ort, Thomas Wagner, Bernd Waidhas | 2020-05-26 |
| 10546817 | Face-up fan-out electronic package with passive components using a support | Thomas Ort, Thomas Wagner, Bernd Waidhas | 2020-01-28 |
| 10403580 | Molded substrate package in fan-out wafer level package | Thomas Ort, Thomas Wagner, Bernd Waidhas | 2019-09-03 |
| 10163687 | System, apparatus, and method for embedding a 3D component with an interconnect structure | David Fraser Rae, Reynante Tamunan Alvarado | 2018-12-25 |
| 10141202 | Semiconductor device comprising mold for top side and sidewall protection | Reynante Tamunan Alvarado, Jianwen Xu | 2018-11-27 |
| 9985010 | System, apparatus, and method for embedding a device in a faceup workpiece | David Fraser Rae, Reynante Tamunan Alvarado | 2018-05-29 |
| 9806048 | Planar fan-out wafer level packaging | David Fraser Rae, Reynante Tamunan Alvarado | 2017-10-31 |
| 9806052 | Semiconductor package interconnect | Reynante Tamunan Alvarado | 2017-10-31 |
| 9679873 | Low profile integrated circuit (IC) package comprising a plurality of dies | David Fraser Rae, Piyush Gupta | 2017-06-13 |
| 9601472 | Package on package (POP) device comprising solder connections between integrated circuit device packages | David Fraser Rae | 2017-03-21 |
| 9379065 | Crack stopping structure in wafer level packaging (WLP) | Zhongping Bao, Reynante Tamunan Alvarado | 2016-06-28 |
| 9318405 | Wafer level package without sidewall cracking | Jianwen Xu, William Stone, Steve Joseph Bezuk, Nicholas Yu | 2016-04-19 |
| 9209110 | Integrated device comprising wires as vias in an encapsulation layer | Reynante Tamunan Alvarado, Steve Joseph Bezuk | 2015-12-08 |