Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Thomas Wagner — 44 Patents

Intel: 42 patents #831 of 30,777Top 3%
Robert Bosch Gmbh: 1 patents #10,465 of 19,740Top 55%
Infineon Technologies Ag: 1 patents #4,631 of 7,486Top 65%
Regelsbach, DE: #1 of 1 inventorsTop 100%
Overall (All Time): #66,838 of 4,157,543Top 2%
44 Patents All Time
Thomas Wagner has been granted 44 US patents while listed as an inventor at Intel. The first was granted in 2011 and the most recent in September 2025. Thomas Wagner ranks #66,838 of 4,157,543 US inventors in our database (top 1.6%). Patent records list Thomas Wagner in Regelsbach, DE.

Issued Patents All Time

Showing 1–25 of 44 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12431424 Buried power rails integrated with decoupling capacitance Bernd Waidhas, Harald Gossner, Wolfgang Molzer, Georg Seidemann, Michael Langenbuch +3 more 2025-09-30
12406925 Bare-die smart bridge connected with copper pillars for system-in-package apparatus Georg Seidemann, Andreas Wolter, Bernd Waidhas 2025-09-02
12362241 Semiconductor structure and method for forming a semiconductor structure Richard Geiger, Klaus Herold, Harald Gossner, Martin Ostermayr, Georgios Panagopoulos +2 more 2025-07-15
12362251 Fan out package with integrated peripheral devices and methods Lizabeth Keser, Bernd Waidhas, Thomas Ort 2025-07-15
12341096 Bare-die smart bridge connected with copper pillars for system-in-package apparatus Georg Seidemann, Andreas Wolter, Bernd Waidhas 2025-06-24
12308335 Integrating and accessing passive components in wafer-level packages Gianni SIGNORINI, Veronica Sciriha 2025-05-20
12125815 Assembly of 2XD module using high density interconnect bridges Bernd Waidhas, Andreas Wolter, Georg Seidemann 2024-10-22 $18,859,000
12057364 Package formation methods including coupling a molded routing layer to an integrated routing layer Lizabeth Keser, Thomas Ort, Bernd Waidhas 2024-08-06 $17,070,000
11990408 WLCSP reliability improvement for package edges including package shielding Jan Proschwitz 2024-05-21 $18,840,000
11955395 Fan out package with integrated peripheral devices and methods Lizabeth Keser, Bernd Waidhas, Thomas Ort 2024-04-09 $27,197,000
11764187 Semiconductor packages, and methods for forming semiconductor packages Bernd Waidhas, Georg Seidemann, Andreas Wolter, Andreas Augustin, Sonja Koller +2 more 2023-09-19 $20,015,000
11646288 Integrating and accessing passive components in wafer-level packages Gianni SIGNORINI, Veronica Sciriha 2023-05-09 $19,706,000
11581287 Chip scale thin 3D die stacked package Robert L. Sankman, Sanka Ganesan, Bernd Waidhas, Lizabeth Keser 2023-02-14 $12,790,000
11508637 Fan out package and methods Lizabeth Keser, Thomas Ort, Bernd Waidhas 2022-11-22 $12,862,000
11469213 Systems, methods, and apparatuses for implementing reduced height semiconductor packages for mobile electronics Georg Seidemann, Klaus Reingruber, Bernd Waidhas, Andreas Wolter 2022-10-11 $16,542,000
11404339 Fan out package with integrated peripheral devices and methods Lizabeth Keser, Bernd Waidhas, Thomas Ort 2022-08-02 $13,520,000
11374323 Patch antennas stitched to systems in packages and methods of assembling same Andreas Augustin, Sonja Koller, Bernd Waidhas, Georg Seidemann, Andreas Wolter +2 more 2022-06-28 $15,065,000
11270941 Bare-die smart bridge connected with copper pillars for system-in-package apparatus Georg Seidemann, Andreas Wolter, Bernd Waidhas 2022-03-08 $16,017,000
11211337 Face-up fan-out electronic package with passive components using a support Lizabeth Keser, Thomas Ort, Bernd Waidhas 2021-12-28 $27,770,000
11177220 Vertical and lateral interconnects between dies Georg Seidemann, Andreas Wolter, Bernd Waidhas 2021-11-16 $23,453,000
11127813 Semiconductor inductors Georg Seidemann, Bernd Waidhas, Andreas Wolter, Andreas Augustin 2021-09-21 $30,488,000
11107763 Interconnect structure for stacked die in a microelectronic device Andreas Wolter, Georg Seidemann 2021-08-31 $22,590,000
11018114 Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory Bernd Waidhas, Georg Seidemann, Andreas Augustin, Laurent Millou, Andreas Wolter +2 more 2021-05-25
10816742 Integrated circuit packages including an optical redistribution layer Georg Seidemann, Christian Geissler, Sven Albers, Marc Dittes, Klaus Reingruber +2 more 2020-10-27
10756042 Multi-layer redistribution layer for wafer-level packaging 2020-08-25