Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12107581 | Clock gating circuit and method of operating the same | Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Hui-Zhong Zhuang +1 more | 2024-10-01 |
| 12040800 | Low hold multi-bit flip-flop | Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Shao-Lun Chien | 2024-07-16 |
| 12009824 | Clock gating circuit and method of operating the same | Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Hui-Zhong Zhuang +1 more | 2024-06-11 |
| 11558040 | Low hold multi-bit flip-flop | Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Shao-Lun Chien | 2023-01-17 |
| 11545965 | Clock gating circuit and method of operating the same | Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chen, Hui-Zhong Zhuang +1 more | 2023-01-03 |
| 11508725 | Layout construction for addressing electromigration | Michael Brunolli, Christine Hau-Riege, Mickael Malabry, Sucheta Kumar Harish, Prathiba Balasubramanian +4 more | 2022-11-22 |
| 11437375 | Layout construction for addressing electromigration | Animesh Datta, Ohsang Kwon | 2022-09-06 |
| 10600785 | Layout construction for addressing electromigration | Michael Brunolli, Christine Hau-Riege, Mickael Malabry, Sucheta Kumar Harish, Prathiba Balasubramanian +4 more | 2020-03-24 |
| 10580774 | Layout construction for addressing electromigration | Animesh Datta, Ohsang Kwon | 2020-03-03 |
| 10074609 | Layout construction for addressing electromigration | Animesh Datta, Ohsang Kwon | 2018-09-11 |
| 9990984 | Pulse-stretcher clock generator circuit for high speed memory subsystems | Dorav Kumar, Venkat Narayanan, Bilal Zafar, Venugopal Boynapalli | 2018-06-05 |
| 9979381 | Semi-data gated flop with low clock power/low internal power with minimal area overhead | Xiangdong Chen, Venugopal Boynapalli | 2018-05-22 |
| 9972624 | Layout construction for addressing electromigration | Michael Brunolli, Christine Hau-Riege, Mickael Malabry, Sucheta Kumar Harish, Prathiba Balasubramanian +4 more | 2018-05-15 |
| 9859891 | Standard cell architecture for reduced parasitic resistance and improved datapath speed | Dorav Kumar, Venkatasubramanian Narayanan, Bala Krishna Thalla, Radhika Vinayak Guttal, Sivakumar Paturi | 2018-01-02 |
| 9786663 | Layout construction for addressing electromigration | Animesh Datta, Ohsang Kwon | 2017-10-10 |
| 9755618 | Low-area low clock-power flip-flop | Xiangdong Chen, Venugopal Boynapalli | 2017-09-05 |
| 9673786 | Flip-flop with reduced retention voltage | Animesh Datta, Jay M. Shah, Martin Saint-Laurent, Peeyush Kumar Parkar, Sachin Bapat +3 more | 2017-06-06 |
| 9577635 | Clock-gating cell with low area, low power, and low setup time | Steven James Dillen, Animesh Datta | 2017-02-21 |
| 9318476 | High performance standard cell with continuous oxide definition and characterized leakage current | Xiangdong Chen, Ohsang Kwon, Foua Vang, Animesh Datta | 2016-04-19 |
| 9020084 | High frequency synchronizer | Animesh Datta, Saravanan Marimuthu, Ohsang Kwon | 2015-04-28 |