Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10490242 | Apparatus and method of clock shaping for memory | Masoud Zamani, Bilal Zafar | 2019-11-26 |
| 10163474 | Apparatus and method of clock shaping for memory | Masoud Zamani, Bilal Zafar | 2018-12-25 |
| 10103626 | Digital power multiplexor | Dorav Kumar, Ramaprasath Vilangudipitchai, Venugopal Boynapalli | 2018-10-16 |
| 9979394 | Pulse-generator | Qi Ye, Animesh Datta, Venugopal Boynapalli | 2018-05-22 |
| 9859891 | Standard cell architecture for reduced parasitic resistance and improved datapath speed | Dorav Kumar, Bala Krishna Thalla, Seid Hadi Rasouli, Radhika Vinayak Guttal, Sivakumar Paturi | 2018-01-02 |
| 9852859 | Adjustable power rail multiplexing | Lipeng Cao, Dorav Kumar, Bilal Zafar, Ramaprasath Vilangudipitchai, Xi Luo | 2017-12-26 |
| 9564210 | Aging sensor for a static random access memory (SRAM) | Alex Dongkyu Park | 2017-02-07 |
| 9330785 | Read operation based aging sensor for static random access memory (SRAM) | Keith Alan Bowman, Alex Dongkyu Park, Francois Ibrahim Atallah | 2016-05-03 |
| 9165641 | Process tolerant current leakage reduction in static random access memory (SRAM) | Chirag Gulati, Ashish Akhilesh | 2015-10-20 |
| 9087579 | Sense amplifiers employing control circuitry for decoupling resistive memory sense inputs during state sensing to prevent current back injection, and related methods and systems | Wenqing Wu, Kendrick Hoy Leong Yuen | 2015-07-21 |
| 9081060 | Buffer testing for reconfigurable instruction cell arrays | Hari M. Rao, Venugopal Boynapalli, Sagar Suresh Sabade, Bilal Zafar | 2015-07-14 |
| 8829965 | System and method to perform scan testing using a pulse latch with a blocking gate | Kashyap Ramachandra Bellur | 2014-09-09 |
| 8613025 | Method and apparatus for selecting one of a plurality of video channels for viewings | Padma Lakshmi Anoop Kulkarni, Sajid Saiyed, Vijayan Venkataraman, Sanjay Purushottam Bhat | 2013-12-17 |