Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9673786 | Flip-flop with reduced retention voltage | Seid Hadi Rasouli, Animesh Datta, Jay M. Shah, Martin Saint-Laurent, Peeyush Kumar Parkar +3 more | 2017-06-06 |
| 9053773 | Method and apparatus for clock power saving in multiport latch arrays | Saravanan Marimuthu, Sakthivel PACKIRISAMY | 2015-06-09 |