Issued Patents All Time
Showing 25 most recent of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12230154 | Guiding an unmanned aerial vehicle using multi-point guidance | Shawn S. Keshmiri, Thomas Brendan Le Pichon | 2025-02-18 |
| 10964799 | FinFETs and methods for forming the same | — | 2021-03-30 |
| 10559501 | Self-aligned quadruple patterning process for Fin pitch below 20nm | Stanley Seungchul Song, Da Yang, Kern Rim, Choh Fei Yeap | 2020-02-11 |
| 10510872 | FinFETs and methods for forming the same | — | 2019-12-17 |
| 10504840 | Reducing tip-to-tip distance between end portions of metal lines formed in an interconnect layer of an integrated circuit (IC) | — | 2019-12-10 |
| 10497702 | Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells | John Jianhong Zhu, Da Yang | 2019-12-03 |
| 10497625 | Method and apparatus of multi threshold voltage CMOS | Choh Fei Yeap | 2019-12-03 |
| 10439039 | Integrated circuits including a FinFET and a nanostructure FET | Stanley Seungchul Song, Kern Rim, Choh Fei Yeap | 2019-10-08 |
| 10374063 | FinFETs and methods for forming the same | — | 2019-08-06 |
| 10354912 | Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs) | John Jianhong Zhu, Choh Fei Yeap | 2019-07-16 |
| 10347579 | Reducing tip-to-tip distance between end portions of metal lines formed in an interconnect layer of an integrated circuit (IC) | — | 2019-07-09 |
| 10283526 | Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop | John Jianhong Zhu, Mustafa Badaroglu | 2019-05-07 |
| 10163792 | Semiconductor device having an airgap defined at least partially by a protective structure | John Jianhong Zhu, Choh Fei Yeap, Stanley Seungchul Song, Kern Rim | 2018-12-25 |
| 10157992 | Nanowire device with reduced parasitics | Mustafa Badaroglu, Vladimir Machkaoutsan, Stanley Seungchul Song, Matthew Michael Nowak, Choh Fei Yeap | 2018-12-18 |
| 10141305 | Semiconductor devices employing field effect transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts | Haining Yang, Jun Yuan, Kern Rim, Periannan Chidambaram | 2018-11-27 |
| 10115723 | Complementary metal oxide semiconductor (CMOS) devices employing plasma-doped source/drain structures and related methods | — | 2018-10-30 |
| 10102898 | Ferroelectric-modulated Schottky non-volatile memory | Xia Li, Seung H. Kang | 2018-10-16 |
| 10090244 | Standard cell circuits employing high aspect ratio voltage rails for reduced resistance | Mustafa Badaroglu, Da Yang, Periannan Chidambaram | 2018-10-02 |
| 10079293 | Semiconductor device having a gap defined therein | Kern Rim, John Jianhong Zhu, Stanley Seungchul Song, Mustafa Badaroglu, Vladimir Machkaoutsan +2 more | 2018-09-18 |
| 10062763 | Method and apparatus for selectively forming nitride caps on metal gate | Junjing Bao, Haining Yang, Yanxiang Liu | 2018-08-28 |
| 10043796 | Vertically stacked nanowire field effect transistors | Vladimir Machkaoutsan, Stanley Seungchul Song, Mustafa Badaroglu, John Jianhong Zhu, Junjing Bao +3 more | 2018-08-07 |
| 10032678 | Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices | Stanley Seungchul Song, Da Yang, Vladimir Machkaoutsan, Mustafa Badaroglu, Choh Fei Yeap | 2018-07-24 |
| 9985014 | Minimum track standard cell circuits for reduced area | Mustafa Badaroglu, Da Yang | 2018-05-29 |
| 9953979 | Contact wrap around structure | Stanley Seungchul Song, Vladimir Machkaoutsan, Mustafa Badaroglu, Junjing Bao, John Jianhong Zhu +2 more | 2018-04-24 |
| 9941156 | Systems and methods to reduce parasitic capacitance | Shiqun Gu, Vidhya Ramachandran, Christine Hau-Riege, John Jianhong Zhu, Jihong Choi +2 more | 2018-04-10 |