Issued Patents All Time
Showing 26–50 of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9922880 | Method and apparatus of multi threshold voltage CMOS | Choh Fei Yeap | 2018-03-20 |
| 9876123 | Non-volatile one-time programmable memory device | Xia Li, Xiao Lu, Bin Yang, Jun Yuan, Xiaonan Chen +1 more | 2018-01-23 |
| 9871121 | Semiconductor device having a gap defined therein | Kern Rim, John Jianhong Zhu, Stanley Seungchul Song, Mustafa Badaroglu, Vladimir Machkaoutsan +2 more | 2018-01-16 |
| 9824936 | Adjacent device isolation | Vladimir Machkaoutsan, Mustafa Badaroglu, Stanley Seungchul Song, Choh Fei Yeap | 2017-11-21 |
| 9806177 | FinFETs and methods for forming the same | — | 2017-10-31 |
| 9799560 | Self-aligned structure | Stanley Seungchul Song, Kern Rim, Da Yang, John Jianhong Zhu, Junjing Bao +4 more | 2017-10-24 |
| 9793164 | Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices | Vladimir Machkaoutsan, Stanley Seungchul Song, John Jianhong Zhu, Junjing Bao, Mustafa Badaroglu +2 more | 2017-10-17 |
| 9721891 | Integrated circuit devices and methods | Junjing Bao, John Jianhong Zhu, Stanley Seungchul Song, Niladri Narayan Mojumder, Choh Fei Yeap | 2017-08-01 |
| 9653399 | Middle-of-line integration methods and semiconductor devices | John Jianhong Zhu, Da Yang, Stanley Seungchul Song, Kern Rim | 2017-05-16 |
| 9620612 | Intergrated circuit devices including an interfacial dipole layer | Xia Li | 2017-04-11 |
| 9620454 | Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods | John Jianhong Zhu, Kern Rim, Stanley Seungchul Song, Da Yang | 2017-04-11 |
| 9576801 | High dielectric constant/metal gate (HK/MG) compatible floating gate (FG)/ferroelectric dipole non-volatile memory | Xia Li, Zhongze Wang, Bin Yang, Xiaonan Chen, Yu Lu | 2017-02-21 |
| 9564518 | Method and apparatus for source-drain junction formation in a FinFET with in-situ doping | Vladimir Machkaoutsan, Stanley Seungchul Song, Mustafa Badaroglu, Choh Fei Yeap | 2017-02-07 |
| 9543248 | Integrated circuit devices and methods | Junjing Bao, John Jianhong Zhu, Stanley Seungchul Song, Niladri Narayan Mojumder, Choh Fei Yeap | 2017-01-10 |
| 9536973 | Metal-oxide-semiconductor field-effect transistor with metal-insulator-semiconductor contact structure to reduce schottky barrier | — | 2017-01-03 |
| 9508589 | Conductive layer routing | Stanley Seungchul Song, Kern Rim, Zhongze Wang, Xiangdong Chen, Choh Fei Yeap | 2016-11-29 |
| 9508439 | Non-volatile multiple time programmable memory device | Xia Li, Xiao Lu, Matthew Michael Nowak, Seung H. Kang, Xiaonan Chen +2 more | 2016-11-29 |
| 9502283 | Electron-beam (E-beam) based semiconductor device features | Stanley Seungchul Song, Da Yang, Choh Fei Yeap | 2016-11-22 |
| 9502414 | Adjacent device isolation | Vladimir Machkaoutsan, Mustafa Badaroglu, Stanley Seungchul Song, Choh Fei Yeap | 2016-11-22 |
| 9496181 | Sub-fin device isolation | Stanley Seungchul Song, Vladimir Machkaoutsan, Mustafa Badaroglu, Choh Fei Yeap | 2016-11-15 |
| 9478541 | Half node scaling for vertical structures | Stanley Seungchul Song, Kern Rim, Matthew Michael Nowak, Choh Fei Yeap, Roawen Chen | 2016-10-25 |
| 9478490 | Capacitor from second level middle-of-line layer in combination with decoupling capacitors | John Jianhong Zhu, Stanley Seungchul Song, Kern Rim, Zhongze Wang | 2016-10-25 |
| 9478637 | Scaling EOT by eliminating interfacial layers from high-K/metal gates of MOS devices | — | 2016-10-25 |
| 9472453 | Systems and methods of forming a reduced capacitance device | John Jianhong Zhu, Stanley Seungchul Song, Kern Rim, Choh Fei Yeap | 2016-10-18 |
| 9425096 | Air gap between tungsten metal lines for interconnects with reduced RC delay | Shiqun Gu, Matthew Michael Nowak | 2016-08-23 |