Issued Patents All Time
Showing 1–25 of 96 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8723321 | Copper interconnects with improved electromigration lifetime | Jun Zhai, Paul R. Besser, Kok Yong Yiang, Richard C. Blish, II, Christine Hau-Riege | 2014-05-13 |
| 7994047 | Integrated circuit contact system | Ning Cheng, Huade Walter Yao | 2011-08-09 |
| 7755194 | Composite barrier layers with controlled copper interface surface roughness | Amit P. Marathe, Connie P. Wang, Paul L. King | 2010-07-13 |
| 7157795 | Composite tantalum nitride/tantalum copper capping layer | Darrell M. Erb, Steven C. Avanzino | 2007-01-02 |
| 7071564 | Composite tantalum capped inlaid copper with reduced electromigration and reduced stress migration | Darrell M. Erb, Steven C. Avanzino | 2006-07-04 |
| 7071086 | Method of forming a metal gate structure with tuning of work function by silicon incorporation | Paul R. Besser, Minh Van Ngo, James Pan, Jinsong Yin | 2006-07-04 |
| 7060571 | Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate dielectric | Minh Van Ngo, James Pan, Paul R. Besser, Jinsong Yin | 2006-06-13 |
| 7045384 | Method for determining metal work function by formation of Schottky diodes with shadow mask | James Pan | 2006-05-16 |
| 7033888 | Engineered metal gate electrode | James Pan, Paul R. Besser, Minh Van Ngo, Jinsong Yin | 2006-04-25 |
| 7033940 | Method of forming composite barrier layers with controlled copper interface surface roughness | Amit P. Marathe, Connie P. Wang, Paul L. King | 2006-04-25 |
| 7005387 | Method for preventing an increase in contact hole width during contact formation | Dawn Hopper, Hiroyuki Kinoshita | 2006-02-28 |
| 6989604 | Conformal barrier liner in an integrated circuit interconnect | Minh Van Ngo, John Sanchez, Steven C. Avanzino | 2006-01-24 |
| 6979625 | Copper interconnects with metal capping layer and selective copper alloys | Connie P. Wang, Darrell M. Erb | 2005-12-27 |
| 6952052 | Cu interconnects with composite barrier layers for wafer-to-wafer uniformity | Amit P. Marathe, Connie P. Wang | 2005-10-04 |
| 6939793 | Dual damascene integration scheme for preventing copper contamination of dielectric layer | Lu You, Fei Wang | 2005-09-06 |
| 6939803 | Method for forming conductor reservoir volume for integrated circuit interconnects | Amit P. Marathe, Pin-Chin Connie Wang | 2005-09-06 |
| 6893910 | One step deposition method for high-k dielectric and metal gate electrode | Paul R. Besser, Minh Van Ngo, James Pan, Jinsong Yin | 2005-05-17 |
| 6861350 | Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode | Minh Van Ngo, Jinsong Yin, James Pan, Paul R. Besser | 2005-03-01 |
| 6836017 | Protection of low-k ILD during damascene processing with thin liner | Minh Van Ngo, Steven C. Avanzino, John Sanchez, Suzette K. Pangrle | 2004-12-28 |
| 6830998 | Gate dielectric quality for replacement metal gate transistors | James Pan, Paul R. Besser, Minh Van Ngo, Jinsong Yin | 2004-12-14 |
| 6806172 | Physical vapor deposition of nickel | Eric N. Paton, Susan Tover | 2004-10-19 |
| 6730587 | Titanium barrier for nickel silicidation of a gate electrode | Jacques Bertrand, Minh Van Ngo, George Jonathan Kluth | 2004-05-04 |
| 6727592 | Copper interconnect with improved barrier layer | John Sanchez, Darrell M. Erb, Amit P. Marathe | 2004-04-27 |
| 6727560 | Engineered metal gate electrode | James Pan, Paul R. Besser, Minh Van Ngo, Jinsong Yin | 2004-04-27 |
| 6724051 | Nickel silicide process using non-reactive spacer | Minh Van Ngo, George Jonathan Kluth | 2004-04-20 |