Issued Patents All Time
Showing 51–75 of 96 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6525428 | Graded low-k middle-etch stop layer for dual-inlaid patterning | Minh Van Ngo, Steven C. Avanzino, John Sanchez | 2003-02-25 |
| 6525425 | Copper interconnects with improved electromigration resistance and low resistivity | Pin-Chin Connie Wang | 2003-02-25 |
| 6521529 | HDP treatment for reduced nickel silicide bridging | Minh Van Ngo, Ercan Adem, Robert A. Huertas | 2003-02-18 |
| 6518185 | Integration scheme for non-feature-size dependent cu-alloy introduction | Pin-Chin Connie Wang, Fei Wang, Kashmir Sahota, Steven C. Avanzino, Amit P. Marathe +2 more | 2003-02-11 |
| 6509267 | Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer | Suzette K. Pangrle, Connie P. Wang | 2003-01-21 |
| 6507123 | Nickel silicide process using UDOX to prevent silicide shorting | Minh Van Ngo, Jacques Bertrand | 2003-01-14 |
| 6506668 | Utilization of annealing enhanced or repaired seed layer to improve copper interconnect reliability | Connie P. Wang, Steve Avanzino | 2003-01-14 |
| 6495460 | Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface | Jacques Bertrand, George Jonathan Kluth, Minh Van Ngo | 2002-12-17 |
| 6483154 | Nitrogen oxide plasma treatment for reduced nickel silicide bridging | Minh Van Ngo | 2002-11-19 |
| 6472757 | Conductor reservoir volume for integrated circuit interconnects | Amit P. Marathe, Pin-Chin Connie Wang | 2002-10-29 |
| 6468900 | Dual layer nickel deposition using a cobalt barrier to reduce surface roughness at silicide/junction interface | Jacques Bertrand, George Jonathan Kluth, Minh Van Ngo | 2002-10-22 |
| 6465349 | Nitrogen-plasma treatment for reduced nickel silicide bridging | Minh Van Ngo, Paul R. Besser, Robert A. Huertas | 2002-10-15 |
| 6462416 | Gradated barrier layer in integrated circuit interconnects | Amit P. Marathe, Pin-Chin Connie Wang | 2002-10-08 |
| 6462409 | Semiconductor wafer polishing apparatus | Krishnashree Achuthan | 2002-10-08 |
| 6455413 | Pre-fill CMP and electroplating method for integrated circuits | Minh Quoc Tran | 2002-09-24 |
| 6455422 | Densification process hillock suppression method in integrated circuits | Minh Van Ngo | 2002-09-24 |
| 6455938 | Integrated circuit interconnect shunt layer | Pin-Chin Connie Wang, Amit P. Marathe | 2002-09-24 |
| 6451693 | Double silicide formation in polysicon gate without silicide in source/drain extensions | George Jonathan Kluth, Qi Xiang | 2002-09-17 |
| 6440289 | Method for improving seed layer electroplating for semiconductor | Bhanwar Singh, Bharath Rangarajan | 2002-08-27 |
| 6441490 | Low dielectric constant stop layer for integrated circuit interconnects | Minh Van Ngo | 2002-08-27 |
| 6432817 | Tungsten silicide barrier for nickel silicidation of a gate electrode | Jacques Bertrand, Minh Van Ngo, George Jonathan Kluth | 2002-08-13 |
| 6433402 | Selective copper alloy deposition | Pin-Chin Connie Wang, Amit P. Marathe, Diana M. Schonauer | 2002-08-13 |
| 6425991 | Plating system with secondary ring anode for a semiconductor wafer | Minh Quoc Tran | 2002-07-30 |
| 6402909 | Plating system with shielded secondary anode for semiconductor manufacturing | Minh Quoc Tran | 2002-06-11 |
| 6387767 | Nitrogen-rich silicon nitride sidewall spacer deposition | Paul R. Besser, Minh Van Ngo, George Jonathan Kluth | 2002-05-14 |