| 10295404 |
Solar monitoring system for measuring solar radiation intensity |
Joshua David Freeman, Rahul Kumar |
2019-05-21 |
|
| 10055607 |
Security layer and methods for protecting tenant data in a cloud-mediated computing network |
Shiju Sathyadevan, P. Venkat Rangan |
2018-08-21 |
|
| 10057382 |
Intelligent “IoT gateway” |
Shiju Sathyadevan, Bipin Kunjumon, Harikrishnan Pillai |
2018-08-21 |
|
| 9710664 |
Security layer and methods for protecting tenant data in a cloud-mediated computing network |
Shiju Sathyadevan, P. Venkat Rangan |
2017-07-18 |
|
| 7449413 |
Method for effectively removing polysilicon nodule defects |
Kashmir Sahota |
2008-11-11 |
$5,286,000 |
| 7358191 |
Method for decreasing sheet resistivity variations of an interconnect metal layer |
Brad Davis, James J. Xie, Kashmir Sahota |
2008-04-15 |
|
| 7307002 |
Non-critical complementary masking method for poly-1 definition in flash memory device fabrication |
Unsoon Kim, Hiroyuki Kinoshita, Yu Sun, Christopher H. Raeder, Christopher Foster +2 more |
2007-12-11 |
$706,000 |
| 7294573 |
Method for controlling poly 1 thickness and uniformity in a memory array fabrication process |
Unsoon Kim, Kashmir Sahota, Patriz C. Regalado |
2007-11-13 |
|
| 7125776 |
Multi-step chemical mechanical polishing of a gate area in a FinFET |
Shibly S. Ahmed, Haihong Wang, Bin Yu |
2006-10-24 |
$12,982,000 |
| 7077728 |
Method for reducing edge array erosion in a high-density array |
Kashmir Sahota |
2006-07-18 |
$7,111,000 |
| 7052969 |
Method for semiconductor wafer planarization by isolation material growth |
Kashmir Sahota |
2006-05-30 |
$15,789,000 |
| 6989563 |
Flash memory cell with UV protective layer |
Patrick K. Cheung, Cyrus E. Tabery, Jean Y. Yang, Ning Cheng, Minh Van Ngo |
2006-01-24 |
$11,964,000 |
| 6982464 |
Dual silicon layer for chemical mechanical polishing planarization |
Shibly S. Ahmed, Haihong Wang, Bin Yu |
2006-01-03 |
$22,329,000 |
| 6933219 |
Tightly spaced gate formation through damascene process |
Emmanuil H. Lingunis, Minh Van Ngo, Cyrus E. Tabery, Jean Y. Yang |
2005-08-23 |
$8,041,000 |
| 6855607 |
Multi-step chemical mechanical polishing of a gate area in a FinFET |
Shibly S. Ahmed, Haihong Wang, Bin Yu |
2005-02-15 |
$5,967,000 |
| 6812076 |
Dual silicon layer for chemical mechanical polishing planarization |
Shibly S. Ahmed, Haihong Wang, Bin Yu |
2004-11-02 |
$2,431,000 |
| 6770523 |
Method for semiconductor wafer planarization by CMP stop layer formation |
Kashmir Sahota, Jeffrey P. Erhardt, Arvind Halliyal, Minh Van Ngo |
2004-08-03 |
$1,898,000 |
| 6756643 |
Dual silicon layer for chemical mechanical polishing planarization |
Shibly S. Ahmed, Haihong Wang, Bin Yu |
2004-06-29 |
$3,195,000 |
| 6649511 |
Method of manufacturing a seed layer with annealed region for integrated circuit interconnects |
Amit P. Marathe |
2003-11-18 |
$4,875,000 |
| 6613646 |
Methods for reduced trench isolation step height |
Kashmir Sahota |
2003-09-02 |
$4,831,000 |
| 6610577 |
Self-aligned polysilicon polish |
Jack F. Thomas, Unsoon Kim |
2003-08-26 |
$4,773,000 |
| 6607925 |
Hard mask removal process including isolation dielectric refill |
Unsoon Kim, Dawn Hopper, Yider Wu |
2003-08-19 |
$7,296,000 |
| 6605517 |
Method for minimizing nitride residue on a silicon wafer |
Jayendra D. Bhakta, Angela T. Hui |
2003-08-12 |
$3,677,000 |
| 6569747 |
Methods for trench isolation with reduced step height |
Kashmir Sahota |
2003-05-27 |
$3,164,000 |
| 6559546 |
Tin palladium activation with maximized nuclei density and uniformity on barrier material in interconnect structure |
Sergey Lopatin |
2003-05-06 |
$2,132,000 |
