Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for controlling poly 1 thickness and uniformity in a memory array fabrication process

Method for controlling poly 1 thickness and uniformity in a memory array fabrication process

US Patent 7294573 · Granted Nov 13, 2007

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method of forming high-voltage transistor with thin gate poly2024
Method of forming high-voltage transistor with thin gate poly2023
Memory first process flow and device2022
Charge trapping split gate device and method of fabricating same2021
Embedded non-volatile memory device and fabrication method of the same2020
Memory first process flow and device2020
Split-gate flash cell formed on recessed substrate2019
Memory first process flow and device2019
Solar monitoring system for measuring solar radiation intensity2019
Method of forming high-voltage transistor with thin gate poly2019
Manufacturing of FET devices having lightly doped drain and source regions2019
Three dimensional capacitor2018