Issued Patents All Time
Showing 26–50 of 96 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6723635 | Protection low-k ILD during damascene processing with thin liner | Minh Van Ngo, Steven C. Avanzino, John Sanchez, Suzette K. Pangrle | 2004-04-20 |
| 6720225 | Reactive pre-clean using reducing gas during nickel silicide process | Minh Van Ngo | 2004-04-13 |
| 6713392 | Nitrogen oxide plasma treatment for reduced nickel silicide bridging | Minh Van Ngo | 2004-03-30 |
| 6663787 | Use of ta/tan for preventing copper contamination of low-k dielectric layers | Lu You, Pin-Chin Connie Wang | 2003-12-16 |
| 6661067 | Nitrogen-plasma treatment for reduced nickel silicide bridging | Minh Van Ngo, Paul R. Besser, Robert A. Huertas | 2003-12-09 |
| 6657304 | Conformal barrier liner in an integrated circuit interconnect | Minh Van Ngo, John Sanchez, Steven C. Avanzino | 2003-12-02 |
| 6633083 | Barrier layer integrity test | Young-Chang Joo, Todd P. Lukanc | 2003-10-14 |
| 6617176 | METHOD OF DETERMINING BARRIER LAYER EFFECTIVENESS FOR PREVENTING METALLIZATION DIFFUSION BY FORMING A TEST SPECIMEN DEVICE AND USING A METAL PENETRATION MEASUREMENT TECHNIQUE FOR FABRICATING A PRODUCTION SEMICONDUCTOR DEVICE AND A TEST SPECIMEN DEVICE THEREBY FORMED | John Sanchez, Pin-Chin Connie Wang, Paul R. Besser | 2003-09-09 |
| 6605513 | Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing | Eric N. Paton, Ercan Adem, Jacques Bertrand, Paul R. Besser, Matthew S. Buynoski +4 more | 2003-08-12 |
| 6599835 | Testing dielectric and barrier layers for integrated circuit interconnects | Amit P. Marathe | 2003-07-29 |
| 6593237 | Method for manufacturing a low dielectric constant stop layer for integrated circuit interconnects | Minh Van Ngo | 2003-07-15 |
| 6590288 | Selective deposition in integrated circuit interconnects | Pin-Chin Connie Wang, Amit P. Marathe | 2003-07-08 |
| 6586842 | Dual damascene integration scheme for preventing copper contamination of dielectric layer | Lu You, Fei Wang | 2003-07-01 |
| 6586333 | Integrated plasma treatment and nickel deposition and tool for performing same | Minh Van Ngo | 2003-07-01 |
| 6562718 | Process for forming fully silicided gates | Qi Xiang, Ercan Adem, Jacques Bertrand, Paul R. Besser, Matthew S. Buynoski +5 more | 2003-05-13 |
| 6562717 | Semiconductor device having multiple thickness nickel silicide layers | George Jonathan Kluth, Qi Xiang | 2003-05-13 |
| 6555453 | Fully nickel silicided metal gate with shallow junction formed | Qi Xiang, George Jonathan Kluth | 2003-04-29 |
| 6555461 | Method of forming low resistance barrier on low k interconnect | Suzette K. Pangrle, Minh Van Ngo | 2003-04-29 |
| 6548395 | Method of promoting void free copper interconnects | Pin-Chin Connie Wang | 2003-04-15 |
| 6548403 | Silicon oxide liner for reduced nickel silicide bridging | Minh Van Ngo | 2003-04-15 |
| 6545370 | Composite silicon nitride sidewall spacers for reduced nickel silicide bridging | Minh Van Ngo, Paul R. Besser | 2003-04-08 |
| 6541860 | Barrier-to-seed layer alloying in integrated circuit interconnects | Pin-Chin Connie Wang, Joffre F. Bernard | 2003-04-01 |
| 6541866 | Cobalt barrier for nickel silicidation of a gate electrode | Jacques Bertrand, Minh Van Ngo, George Jonathan Kluth | 2003-04-01 |
| 6531780 | Via formation in integrated circuit interconnects | Pin-Chin Connie Wang, Amit P. Marathe | 2003-03-11 |
| 6531777 | Barrier metal integrity testing using a dual level line to line leakage testing pattern and partial CMP | Amit P. Marathe | 2003-03-11 |