Issued Patents All Time
Showing 25 most recent of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10191108 | On-chip sensor for monitoring active circuits on integrated circuit (IC) chips | Siyuranga O. Koswatta, Paul S. McLaughlin, Daniel J. Poindexter, J. Campbell Scott, Scott M. Taylor +2 more | 2019-01-29 |
| 9953873 | Methods of modulating the morphology of epitaxial semiconductor material | Bhupesh Chandra, Claude Ortolland, Viorel Ontalus, Christopher D. Sheraw, Timothy J. McArdle +1 more | 2018-04-24 |
| 9906213 | Reducing thermal runaway in inverter devices | Siyuranga O. Koswatta | 2018-02-27 |
| 9552455 | Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specifications | Daniel J. Poindexter, Siyuranga O. Koswatta, J. Campbell Scott, Leon Sigal, James D. Warnock | 2017-01-24 |
| 9406569 | Semiconductor device having diffusion barrier to reduce back channel leakage | Kam-Leung Lee, Chengwen Pei, Geng Wang, Yanli Zhang | 2016-08-02 |
| 9305999 | Stress-generating structure for semiconductor-on-insulator devices | Huilong Zhu, Brian J. Greene, Dureseti Chidambarrao | 2016-04-05 |
| 9287399 | Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels | Bhupesh Chandra, Paul Chang, Dechao Guo, Judson R. Holt, Arvind Kumar +6 more | 2016-03-15 |
| 9240354 | Semiconductor device having diffusion barrier to reduce back channel leakage | Kam-Leung Lee, Chengwen Pei, Geng Wang, Yanli Zhang | 2016-01-19 |
| 8940595 | Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels | Bhupesh Chandra, Paul Chang, Dechao Guo, Judson R. Holt, Arvind Kumar +6 more | 2015-01-27 |
| 8629501 | Stress-generating structure for semiconductor-on-insulator devices | Huilong Zhu, Brian J. Greene, Dureseti Chidambarrao | 2014-01-14 |
| 8232603 | Gated diode structure and method including relaxed liner | Anthony I. Chou, Kevin McStay, Shreesh Narasimha | 2012-07-31 |
| 8115254 | Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same | Huilong Zhu, Brian J. Greene, Dureseti Chidambarrao | 2012-02-14 |
| 8017483 | Method of creating asymmetric field-effect-transistors | Shreesh Narasimha, Ning Su, Hasan M. Nayfeh, Nivo Rovedo, Werner Rausch +1 more | 2011-09-13 |
| 7863143 | High performance schottky-barrier-source asymmetric MOSFETs | Qingqing Liang, Huilong Zhu | 2011-01-04 |
| 7790553 | Methods for forming high performance gates and structures thereof | Huilong Zhu, Xiaomeng Chen, Mahender Kumar, Brian J. Greene, Bachir Dirahoui +1 more | 2010-09-07 |
| 7749822 | Method of forming a resistor and an FET from the metal portion of a MOSFET metal gate stack | William K. Henson | 2010-07-06 |
| 7741186 | Creating increased mobility in a bipolar device | Dureseti Chidambarrao, Marwan H. Khater | 2010-06-22 |
| 7709930 | Tuneable semiconductor device with discontinuous portions in the sub-collector | Andreas D. Stricker, David C. Sheridan, Jae-Sung Rieh, Steven H. Voldman, Stephen A. St. Onge | 2010-05-04 |
| 7615457 | Method of fabricating self-aligned bipolar transistor having tapered collector | Hiroyuki Akatsu, Rama Divakaruni, David R. Greenberg, Marwan H. Khater, William R. Tonti | 2009-11-10 |
| 7611954 | Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same | Marwan H. Khater, Francois Pagette | 2009-11-03 |
| 7611953 | Bipolar transistor with isolation and direct contacts | David C. Ahlgren, Francois Pagette, Christopher M. Schnabel, Anna W. Topol | 2009-11-03 |
| 7476914 | Methods to improve the SiGe heterojunction bipolar device performance | Omer H. Dokumaci, Marwan H. Khater, Rajendran Krishnasamy, Kathryn T. Schonenberg | 2009-01-13 |
| 7466010 | Bipolar transistor having self-aligned silicide and a self-aligned emitter contact border | David C. Ahlgren, Marwan H. Khater, Richard P. Volant | 2008-12-16 |
| 7442595 | Bipolar transistor with collector having an epitaxial Si:C region | Marwan H. Khater, Rajendran Krishnasamy, Kathryn T. Schonenberg, Andreas D. Stricker | 2008-10-28 |
| 7425754 | Structure and method of self-aligned bipolar transistor having tapered collector | Hiroyuki Akatsu, Rama Divakaruni, David R. Greenberg, Marwan H. Khater, William R. Tonti | 2008-09-16 |