Issued Patents All Time
Showing 1–25 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8659087 | Electronic device with a gate electrode having at least two portions | Tien Ying Luo, Narayanan C. Ramani | 2014-02-25 |
| 8435898 | First inter-layer dielectric stack for non-volatile memory | Christopher B. Hundley, Paul A. Ingersoll, Craig T. Swift | 2013-05-07 |
| 8426310 | Method of forming a shared contact in a semiconductor device | Ted R. White, Mark D. Hall | 2013-04-23 |
| 8404594 | Reverse ALD | Dina H. Triyoso | 2013-03-26 |
| 8125032 | Modified hybrid orientation technology | Mariam Sadaka, Ted R. White, Bich-Yen Nguyen | 2012-02-28 |
| 8030220 | Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer | Dina H. Triyoso | 2011-10-04 |
| 7981808 | Method of forming a gate dielectric by in-situ plasma | Tien Ying Luo | 2011-07-19 |
| 7868389 | Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities | David C. Gilmer, Philip J. Tobin | 2011-01-11 |
| 7811891 | Method to control the gate sidewall profile by graded material composition | Marius Orlowski, Phillip Stout | 2010-10-12 |
| 7745298 | Method of forming a via | Tab A. Stephens, Paul A. Grudowski, Matthew T. Herrick | 2010-06-29 |
| 7704821 | In-situ nitridation of high-k dielectrics | Dina H. Triyoso, Hsing-Huang Tseng | 2010-04-27 |
| 7651935 | Process of forming an electronic device including active regions and gate electrodes of different compositions overlying the active regions | Tien Ying Luo, Narayanan C. Ramani | 2010-01-26 |
| 7618902 | Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer | Dina H. Triyoso | 2009-11-17 |
| 7579282 | Method for removing metal foot during high-k dielectric/metal gate etching | Shahid Rauf, Eric D. Luckowski, Peter L. G. Ventzek | 2009-08-25 |
| 7544575 | Dual metal silicide scheme using a dual spacer process | Dharmesh Jawarani, Randy W. Cotton | 2009-06-09 |
| 7524707 | Modified hybrid orientation technology | Mariam Sadaka, Ted R. White, Bich-Yen Nguyen | 2009-04-28 |
| 7442621 | Semiconductor process for forming stress absorbent shallow trench isolation structures | Marius Orlowski, Mark C. Foisy | 2008-10-28 |
| 7435646 | Method for forming floating gates within NVM process | Jeffrey W. Thomas | 2008-10-14 |
| 7432164 | Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same | David C. Gilmer, Philip J. Tobin | 2008-10-07 |
| 7402472 | Method of making a nitrided gate dielectric | Sangwoo Lim, Paul A. Grudowski, Tien Ying Luo, Hsing-Huang Tseng | 2008-07-22 |
| 7303983 | ALD gate electrode | Dina H. Triyoso, James K. Schaeffer | 2007-12-04 |
| 7297588 | Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities and a process for forming the same | David C. Gilmer, Philip J. Tobin | 2007-11-20 |
| 7297586 | Gate dielectric and metal gate integration | Dina H. Triyoso | 2007-11-20 |
| 7288458 | SOI active layer with different surface orientation | Robert E. Jones, Ted R. White | 2007-10-30 |
| 7235502 | Transitional dielectric layer to improve reliability and performance of high dielectric constant transistors | Sriram Kalpat, Voon-Yew Thean, Hsing-Huang Tseng | 2007-06-26 |