FH

Frederick N. Hause

AM AMD: 106 patents #25 of 9,279Top 1%
Harris: 2 patents #731 of 2,288Top 35%
AP Advanced Microdevices Pvt: 1 patents #2 of 26Top 8%
Overall (All Time): #12,034 of 4,157,543Top 1%
110
Patents All Time

Issued Patents All Time

Showing 25 most recent of 110 patents

Patent #TitleCo-InventorsDate
7220655 Method of forming an alignment mark on a wafer, and a wafer comprising same Jeffrey C. Haines, Michael E. Exterkamp 2007-05-22
6809032 Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques Frank Mauersberger, Peter J. Beckage, Paul R. Besser, Errol Todd Ryan, William S. Brennan +1 more 2004-10-26
6661057 Tri-level segmented control transistor and fabrication method Robert Dawson, Mark I. Gardner, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more 2003-12-09
6555479 Method for forming openings for conductive interconnects Paul R. Besser, Frank Mauersberger, Errol Todd Ryan, William S. Brennan, John A. Iacoponi +1 more 2003-04-29
6555892 Semiconductor device with reduced line-to-line capacitance and cross talk noise Manfred Horstmann, Karsten Wieczorek 2003-04-29
6552776 Photolithographic system including light filter that compensates for lens error Derick J. Wristers, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Bradley T. Moore +1 more 2003-04-22
6514858 Test structure for providing depth of polish feedback Paul R. Besser, Frank Mauersberger, Errol Todd Ryan, William S. Brennan, John A. Iacoponi +1 more 2003-02-04
6491799 Method for forming a thin dielectric layer Karsten Wieczorek, Manfred Horstmann 2002-12-10
6489240 Method for forming copper interconnects John A. Iacoponi, Paul R. Besser, Frank Mauersberger, Errol Todd Ryan, William S. Brennan +1 more 2002-12-03
6458678 Transistor formed using a dual metal process for gate and source/drain region Thomas E. Spikes, Jr., David Wu 2002-10-01
6429052 Method of making high performance transistor with a reduced width gate electrode and device comprising same Mark I. Gardner, John J. Bush 2002-08-06
6426262 Method of analyzing the effects of shadowing of angled halo implants Mark B. Fuselier, Jon D. Cheek, Marilyn I. Wright 2002-07-30
6413846 Contact each methodology and integration scheme Paul R. Besser, Errol Todd Ryan, Frank Mauersberger, William S. Brennan, John A. Iacoponi +1 more 2002-07-02
6410409 Implanted barrier layer for retarding upward diffusion of substrate dopant Mark I. Gardner, Robert Dawson, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more 2002-06-25
6410967 Transistor having enhanced metal silicide and a self-aligned gate electrode Mark I. Gardner, Charles E. May 2002-06-25
6403445 Enhanced trench isolation structure Mark I. Gardner, Charles E. May 2002-06-11
6380055 Dopant diffusion-retarding barrier region formed within polysilicon gate layer Mark I. Gardner, Robert Dawson, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more 2002-04-30
6376350 Method of forming low resistance gate electrode Michael Duane, Jeffrey C. Haines 2002-04-23
6372588 Method of making an IGFET using solid phase diffusion to dope the gate, source and drain Derick J. Wristers, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Mark W. Michael +1 more 2002-04-16
6358826 Device improvement by lowering LDD resistance with new spacer/silicide process Manfred Horstmann, Karsten Wieczorek 2002-03-19
6352885 Transistor having a peripherally increased gate insulation thickness and a method of fabricating the same Karsten Wieczorek, Manfred Horstmann 2002-03-05
6346463 Method for forming a semiconductor device with a tailored well profile Akif Sultan 2002-02-12
6337217 Method and apparatus for improved focus in optical processing Karen Turnquest 2002-01-08
6274894 Low-bandgap source and drain formation for short-channel MOS transistors Karsten Wieczorek, Manfred Horstmann 2001-08-14
6268637 Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication Mark I. Gardner, Charles E. May 2001-07-31