Issued Patents All Time
Showing 25 most recent of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12316251 | Variable-speed drive for single-phase asynchronous motors | — | 2025-05-27 |
| 8440516 | Method of forming a field effect transistor | Andy Wei, Thorsten Kammler, Jan Hoentschel | 2013-05-14 |
| 8288256 | Enhancing transistor characteristics by a late deep implantation in combination with a diffusion-free anneal process | Thomas Feudel, Rolf Stephan | 2012-10-16 |
| 8274120 | Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions | Andy Wei, Thorsten Kammler, Jan Hoentschel, Peter Javorka, Joe Bloomquist | 2012-09-25 |
| 8188871 | Drive current adjustment for transistors by local gate engineering | Patrick Press, Karsten Wieczorek, Kerstin Ruttloff | 2012-05-29 |
| 8138571 | Semiconductor device comprising isolation trenches inducing different types of strain | Christoph Schwan, Joe Bloomquist, Peter Javorka, Sven Beyer, Markus Forsberg +2 more | 2012-03-20 |
| 8101512 | Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography | Martin Gerhardt, Martin Trentzsch, Markus Forsberg | 2012-01-24 |
| 8097542 | Etch stop layer of reduced thickness for patterning a dielectric material in a contact level of closely spaced transistors | Karsten Wieczorek, Peter Huebler, Kerstin Ruttloff | 2012-01-17 |
| 8039335 | Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain | Sven Beyer, Patrick Press, Wolfgang Buchholtz | 2011-10-18 |
| 8039338 | Method for reducing defects of gate of CMOS devices during cleaning processes by modifying a parasitic PN junction | Peter Javorka, Karsten Wieczorek, Kerstin Ruttloff | 2011-10-18 |
| 7999326 | Tensile strain source using silicon/germanium in globally strained silicon | Andy Wei, Karla Romero | 2011-08-16 |
| 7955937 | Method for manufacturing semiconductor device comprising SOI transistors and bulk transistors | Karsten Wieczorek, Thomas Feudel, Thomas J. Heller, Jr. | 2011-06-07 |
| 7906383 | Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device | Ralf Richter, Andy Wei, Joerg Hohage | 2011-03-15 |
| 7893503 | Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain | Sven Beyer, Patrick Press, Wolfgang Buchholtz | 2011-02-22 |
| 7863171 | SOI transistor having a reduced body potential and a method of forming the same | Jan Hoentschel, Andy Wei, Joe Bloomquist | 2011-01-04 |
| 7829421 | SOI transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same | Andy Wei, Thorsten Kammler, Jan Hoentschel | 2010-11-09 |
| 7816199 | Method of forming a semiconductor structure comprising an implantation of ions of a non-doping element | Thomas Feudel, Andreas Gehring | 2010-10-19 |
| 7763515 | Transistor with embedded silicon/germanium material on a strained semiconductor on insulator substrate | Andy Wei, Thorsten Kammler, Roman Boschke | 2010-07-27 |
| 7741167 | Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain | Sven Beyer, Patrick Press, Wolfgang Buchholtz | 2010-06-22 |
| 7732291 | Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regions | Joe Bloomquist, Peter Javorka, Gert Burbach | 2010-06-08 |
| 7727827 | Method of forming a semiconductor structure | Frank Wirbeleit, Rolf Stephan | 2010-06-01 |
| 7723195 | Method of forming a field effect transistor | Andy Wei, Thorsten Kammler, Jan Hoentschel | 2010-05-25 |
| 7719060 | Tensile strain source using silicon/germanium in globally strained silicon | Andy Wei, Karla Romero | 2010-05-18 |
| 7696052 | Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions | Andy Wei, Thorsten Kammler, Jan Hoentschel, Peter Javorka, Joe Bloomquist | 2010-04-13 |
| 7659213 | Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same | Andy Wei, Thorsten Kammler, Jan Hoentschel | 2010-02-09 |