Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Manfred Horstmann — 84 Patents

AMD: 74 patents #63 of 9,280Top 1%
Globalfoundries: 9 patents #393 of 4,424Top 9%
Pasadena, CA: #13 of 3,212 inventorsTop 1%
California: #3,153 of 386,348 inventorsTop 1%
Overall (All Time): #20,511 of 4,157,543Top 1%
84 Patents All Time
Manfred Horstmann has been granted 84 US patents while listed as an inventor at AMD. The first was granted in 2000 and the most recent in May 2025. Manfred Horstmann ranks #20,511 of 4,157,543 US inventors in our database (top 0.49%). Patent records list Manfred Horstmann in Pasadena, CA, US.

Issued Patents All Time

Showing 1–25 of 84 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12316251 Variable-speed drive for single-phase asynchronous motors 2025-05-27
8440516 Method of forming a field effect transistor Andy Wei, Thorsten Kammler, Jan Hoentschel 2013-05-14 $3,052,000
8288256 Enhancing transistor characteristics by a late deep implantation in combination with a diffusion-free anneal process Thomas Feudel, Rolf Stephan 2012-10-16 $3,691,000
8274120 Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions Andy Wei, Thorsten Kammler, Jan Hoentschel, Peter Javorka, Joe Bloomquist 2012-09-25 $4,174,000
8188871 Drive current adjustment for transistors by local gate engineering Patrick Press, Karsten Wieczorek, Kerstin Ruttloff 2012-05-29 $10,485,000
8138571 Semiconductor device comprising isolation trenches inducing different types of strain Christoph Schwan, Joe Bloomquist, Peter Javorka, Sven Beyer, Markus Forsberg +2 more 2012-03-20 $9,207,000
8101512 Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography Martin Gerhardt, Martin Trentzsch, Markus Forsberg 2012-01-24 $3,915,000
8097542 Etch stop layer of reduced thickness for patterning a dielectric material in a contact level of closely spaced transistors Karsten Wieczorek, Peter Huebler, Kerstin Ruttloff 2012-01-17 $6,179,000
8039335 Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain Sven Beyer, Patrick Press, Wolfgang Buchholtz 2011-10-18 $1,986,000
8039338 Method for reducing defects of gate of CMOS devices during cleaning processes by modifying a parasitic PN junction Peter Javorka, Karsten Wieczorek, Kerstin Ruttloff 2011-10-18 $1,986,000
7999326 Tensile strain source using silicon/germanium in globally strained silicon Andy Wei, Karla Romero 2011-08-16 $3,370,000
7955937 Method for manufacturing semiconductor device comprising SOI transistors and bulk transistors Karsten Wieczorek, Thomas Feudel, Thomas J. Heller, Jr. 2011-06-07 $10,131,000
7906383 Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device Ralf Richter, Andy Wei, Joerg Hohage 2011-03-15 $6,095,000
7893503 Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain Sven Beyer, Patrick Press, Wolfgang Buchholtz 2011-02-22 $17,676,000
7863171 SOI transistor having a reduced body potential and a method of forming the same Jan Hoentschel, Andy Wei, Joe Bloomquist 2011-01-04 $12,328,000
7829421 SOI transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same Andy Wei, Thorsten Kammler, Jan Hoentschel 2010-11-09 $4,649,000
7816199 Method of forming a semiconductor structure comprising an implantation of ions of a non-doping element Thomas Feudel, Andreas Gehring 2010-10-19 $4,223,000
7763515 Transistor with embedded silicon/germanium material on a strained semiconductor on insulator substrate Andy Wei, Thorsten Kammler, Roman Boschke 2010-07-27 $6,860,000
7741167 Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain Sven Beyer, Patrick Press, Wolfgang Buchholtz 2010-06-22 $10,015,000
7732291 Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regions Joe Bloomquist, Peter Javorka, Gert Burbach 2010-06-08 $16,231,000
7727827 Method of forming a semiconductor structure Frank Wirbeleit, Rolf Stephan 2010-06-01 $11,970,000
7723195 Method of forming a field effect transistor Andy Wei, Thorsten Kammler, Jan Hoentschel 2010-05-25 $6,565,000
7719060 Tensile strain source using silicon/germanium in globally strained silicon Andy Wei, Karla Romero 2010-05-18 $8,134,000
7696052 Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions Andy Wei, Thorsten Kammler, Jan Hoentschel, Peter Javorka, Joe Bloomquist 2010-04-13 $12,774,000
7659213 Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same Andy Wei, Thorsten Kammler, Jan Hoentschel 2010-02-09 $15,199,000