Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8806824 | Wall construction and component for the same | — | 2014-08-19 |
| 8617940 | SOI device with a buried insulating material having increased etch resistivity | Andreas Kurz, Roman Boschke, John Morgan | 2013-12-31 |
| 8609485 | Methods of forming efuse devices | Andreas Kurz, Andy Wei | 2013-12-17 |
| 8564089 | Electronic fuse structure formed using a metal gate electrode material stack configuration | Andreas Kurz, Jan Hoentschel | 2013-10-22 |
| 8193066 | Semiconductor device comprising a silicon/germanium resistor | Andreas Kurz, Roman Boschke, John Morgan | 2012-06-05 |
| 8138571 | Semiconductor device comprising isolation trenches inducing different types of strain | Joe Bloomquist, Peter Javorka, Manfred Horstmann, Sven Beyer, Markus Forsberg +2 more | 2012-03-20 |
| 8110487 | Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region | Uwe Griebenow, Kai Frohberg, Kerstin Ruttloff | 2012-02-07 |
| 7838354 | Method for patterning contact etch stop layers by using a planarization process | Kai Frohberg, Sven Mueller | 2010-11-23 |
| 7838359 | Technique for forming contact insulation layers and silicide regions with different characteristics | Kai Frohberg, Matthias Lehr | 2010-11-23 |
| 7713815 | Semiconductor device including a vertical decoupling capacitor | Matthias Lehr, Kai Frohberg | 2010-05-11 |
| 7659170 | Method of increasing transistor drive current by recessing an isolation trench | Manfred Horstmann, Martin Gerhardt, Markus Forseberg | 2010-02-09 |
| 7563731 | Field effect transistor having a stressed dielectric layer based on an enhanced device topography | Manfred Horstmann, Kai Frohberg, Rolf Stephan | 2009-07-21 |
| 7556996 | Field effect transistor comprising a stressed channel region and method of forming the same | Joe Bloomquist, Kai Frohberg, Manfred Horstmann | 2009-07-07 |
| 7547610 | Method of making a semiconductor device comprising isolation trenches inducing different types of strain | Joe Bloomquist, Peter Javorka, Manfred Horstmann, Sven Beyer, Markus Forsberg +2 more | 2009-06-16 |
| 7338872 | Method of depositing a layer of a material on a substrate | Thomas Feudel, Thorsten Kammler | 2008-03-04 |
| 7192881 | Method of forming sidewall spacer elements for a circuit element by increasing an etch selectivity | Thorsten Kammler, Karsten Wieczorek | 2007-03-20 |
| 7098140 | Method of compensating for etch rate non-uniformities by ion implantation | Matthias Schaller, Carsten Hartig | 2006-08-29 |
| 7064071 | Method of forming a conformal spacer adjacent to a gate electrode structure | — | 2006-06-20 |
| 7005358 | Technique for forming recessed sidewall spacers for a polysilicon line | Thorsten Kammler, Katja Huy | 2006-02-28 |
| 7005305 | Signal layer for generating characteristic optical plasma emissions | Gunter Grasshoff, Matthias Schaller | 2006-02-28 |
| 6969676 | Method of adjusting etch selectivity by adapting aspect ratios in a multi-level etch process | Gunter Grasshoff, Volker Grimm | 2005-11-29 |
| 6696334 | Method for formation of a differential offset spacer | Kay Hellig, Srikanteswara Dakshina-Murthy | 2004-02-24 |
| 6579801 | Method for enhancing shallow trench top corner rounding using endpoint control of nitride layer etch process with appropriate etch front | Srikanteswara Dakshina-Murthy, Jeffrey C. Haines | 2003-06-17 |