Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8987103 | Multi-step deposition of a spacer material for reducing void formation in a dielectric material of a contact level of a semiconductor device | Markus Lenski, Volker Jaschke, Frank Seliger, Ralf Otterbach | 2015-03-24 |
| 8772843 | Oxide deposition by using a double liner approach for reducing pattern density dependence in sophisticated semiconductor devices | Stephan Kronholz, Markus Lenski, Volker Jaschke | 2014-07-08 |
| 8709902 | Sacrificial spacer approach for differential source/drain implantation spacers in transistors comprising a high-k metal gate electrode structure | Thilo Scheiper, Maciej Wiatr, Stefan Flachowsky | 2014-04-29 |
| 8440534 | Threshold adjustment for MOS devices by adapting a spacer width prior to implantation | Uwe Griebenow, Jan Hoentschel, Kai Frohberg, Heike Berthold, Katrin Reiche +1 more | 2013-05-14 |
| 8436425 | SOI semiconductor device comprising substrate diodes having a topography tolerant contact structure | Jens Heinrich, Kai Frohberg | 2013-05-07 |
| 8318598 | Contacts and vias of a semiconductor device formed by a hard mask and double exposure | Sven Beyer, Kai Frohberg, Katrin Reiche | 2012-11-27 |
| 8188871 | Drive current adjustment for transistors by local gate engineering | Manfred Horstmann, Patrick Press, Karsten Wieczorek | 2012-05-29 |
| 8110487 | Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region | Uwe Griebenow, Kai Frohberg, Christoph Schwan | 2012-02-07 |
| 8097542 | Etch stop layer of reduced thickness for patterning a dielectric material in a contact level of closely spaced transistors | Karsten Wieczorek, Manfred Horstmann, Peter Huebler | 2012-01-17 |
| 8048726 | SOI semiconductor device with reduced topography above a substrate window area | Jens Heinrich, Kai Frohberg, Sven Mueller | 2011-11-01 |
| 8039338 | Method for reducing defects of gate of CMOS devices during cleaning processes by modifying a parasitic PN junction | Manfred Horstmann, Peter Javorka, Karsten Wieczorek | 2011-10-18 |
| 7981740 | Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning | Markus Lenski, Martin Mazur, Frank Seliger, Ralf Otterbach | 2011-07-19 |