KF

Kai Frohberg

Globalfoundries: 47 patents #46 of 4,424Top 2%
AM AMD: 43 patents #181 of 9,279Top 2%
📍 Meißen, DE: #1 of 42 inventorsTop 3%
Overall (All Time): #18,058 of 4,157,543Top 1%
90
Patents All Time

Issued Patents All Time

Showing 1–25 of 90 patents

Patent #TitleCo-InventorsDate
9761689 Method of forming a semiconductor device and according semiconductor device Dominic Thurmer, Hans-Juergen Thees, Peter Moll, Heike Scholz 2017-09-12
9590056 Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers Marco Lepper, Katrin Reiche 2017-03-07
9269809 Methods for forming protection layers on sidewalls of contact etch stop layers Marco Lepper, Katrin Reiche 2016-02-23
9245860 Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom Frank Feustel, Thomas Werner 2016-01-26
9196684 Tensile nitride profile shaper etch to provide void free gapfill Peter Moll, Dominik Olligs, Heike Scholz 2015-11-24
9159661 Integrated circuits with close electrical contacts and methods for fabricating the same Peter Moll, Heike Scholz 2015-10-13
9153684 Semiconductor fuses in a semiconductor device comprising metal gates Jens Heinrich, Ralf Richter 2015-10-06
9006114 Method for selectively removing a spacer in a dual stress liner approach Volker Grimm, Heike Salz, Heike Berthold 2015-04-14
8941182 Buried sublevel metallizations for improved transistor density Dominik Olligs, Jens Heinrich, Katrin Reiche 2015-01-27
8883582 High-K gate electrode structure formed after transistor fabrication by using a spacer Uwe Griebenow, Katrin Reiche, Heike Berthold 2014-11-11
8877597 Embedding metal silicide contact regions reliably into highly doped drain and source regions by a stop implantation Jens Heinrich, Frank Feustel 2014-11-04
8859418 Methods of forming conductive structures using a dual metal hard mask technique Torsten Huisinga, Jens Hahn 2014-10-14
8859398 Enhancing adhesion of interlayer dielectric materials of semiconductor devices by suppressing silicide formation at the substrate edge Tobias Letz, Frank Feustel 2014-10-14
8835303 Metallization system of a semiconductor device comprising extra-tapered transition vias Frank Feustel, Thomas Werner 2014-09-16
8828887 Restricted stress regions formed in the contact level of a semiconductor device Frank Feustel, Thomas Werner 2014-09-09
8786088 Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction Torsten Huisinga, Jens Heinrich, Frank Feustel 2014-07-22
8772178 Technique for forming a dielectric interlayer above a structure including closely spaced lines Hartmut Ruelke, Christof Streck 2014-07-08
8735237 Method for increasing penetration depth of drain and source implantation species for a given gate height Uwe Griebenow, Frank Feustel, Thomas Werner 2014-05-27
8722511 Reduced topography in isolation regions of a semiconductor device by applying a deposition/etch sequence prior to forming the interlayer dielectric Ralf Richter, Peter Javorka 2014-05-13
8673696 SOI semiconductor device comprising a substrate diode with reduced metal silicide leakage Peter Baars, Frank Jakubowski, Jens Heinrich, Marco Lepper, Jana Schlott 2014-03-18
8658494 Dual contact metallization including electroless plating in a semiconductor device Juergen Boemmels, Matthias Schaller, Sven Mueller 2014-02-25
8615145 Semiconductor device comprising a buried waveguide for device internal optical communication Uwe Griebenow, Jan Hoentschel 2013-12-24
8609524 Method for making semiconductor device comprising replacement gate electrode structures with an enhanced diffusion barrier Frank Feustal, Thomas Werner 2013-12-17
8580684 Contact elements of semiconductor devices comprising a continuous transition to metal lines of a metallization layer Robert Seidel, Carsten Peters 2013-11-12
8536052 Semiconductor device comprising contact elements with silicided sidewall regions Jens Heinrich, Katrin Reiche 2013-09-17