Issued Patents All Time
Showing 26–50 of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8536052 | Semiconductor device comprising contact elements with silicided sidewall regions | Jens Heinrich, Katrin Reiche | 2013-09-17 |
| 8492269 | Hybrid contact structure with low aspect ratio contacts in a semiconductor device | Jens Heinrich, Ralf Richter, Torsten Huisinga | 2013-07-23 |
| 8492217 | Methods of forming conductive contacts with reduced dimensions | Dominik Olligs, Daniel Prochnow, Katrin Reiche | 2013-07-23 |
| 8470661 | High-K gate electrode structure formed after transistor fabrication by using a spacer | Uwe Griebenow, Katrin Reiche, Heike Berthold | 2013-06-25 |
| 8440534 | Threshold adjustment for MOS devices by adapting a spacer width prior to implantation | Uwe Griebenow, Jan Hoentschel, Heike Berthold, Katrin Reiche, Frank Feustel +1 more | 2013-05-14 |
| 8436425 | SOI semiconductor device comprising substrate diodes having a topography tolerant contact structure | Jens Heinrich, Kerstin Ruttloff | 2013-05-07 |
| 8384161 | Contact optimization for enhancing stress transfer in closely spaced transistors | Ralf Richter, Holger Schuehrer | 2013-02-26 |
| 8377820 | Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via size | Thomas Werner, Frank Feustel | 2013-02-19 |
| 8368221 | Hybrid contact structure with low aspect ratio contacts in a semiconductor device | Frank Feustel, Thomas Werner | 2013-02-05 |
| 8367504 | Method for forming semiconductor fuses in a semiconductor device comprising metal gates | Jens Heinrich, Ralf Richter | 2013-02-05 |
| 8361844 | Method for adjusting the height of a gate electrode in a semiconductor device | Heike Berthold, Katrin Reiche, Uwe Griebenow | 2013-01-29 |
| 8357610 | Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics | Frank Feustel, Thomas Werner, Michael Grillberger | 2013-01-22 |
| 8349744 | Double deposition of a stress-inducing layer in an interlayer dielectric with intermediate stress relaxation in a semiconductor device | Uwe Griebenow, Katrin Reiche, Heike Berthold | 2013-01-08 |
| 8338284 | Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacer | Hartmut Ruelke, Volker Jaschke, Joerg Hohage, Frank Seliger | 2012-12-25 |
| 8318598 | Contacts and vias of a semiconductor device formed by a hard mask and double exposure | Sven Beyer, Katrin Reiche, Kerstin Ruttloff | 2012-11-27 |
| 8241973 | Method for increasing penetration depth of drain and source implantation species for a given gate height | Uwe Griebenow, Frank Feustel, Thomas Werner | 2012-08-14 |
| 8216927 | Method of reducing contamination by providing a removable polymer protection film during microstructure processing | Ralf Richter, Frank Feustel, Thomas Werner | 2012-07-10 |
| 8198147 | Superior fill conditions in a replacement gate approach by using a tensile stressed overlayer | Frank Feustel, Thomas Werner | 2012-06-12 |
| 8129276 | Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistors | Ralf Richter, Holger Schuehrer | 2012-03-06 |
| 8110487 | Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region | Uwe Griebenow, Christoph Schwan, Kerstin Ruttloff | 2012-02-07 |
| 8105962 | Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approach | Frank Feustel, Thomas Werner, Uwe Griebenow | 2012-01-31 |
| 8101524 | Technique for enhancing the fill capabilities in an electrochemical deposition process by edge rounding of trenches | Matthias Schaller, Massud Aminpur | 2012-01-24 |
| 8048736 | Semiconductor device comprising a capacitor in the metallization system and a method of forming the capacitor | Thomas Werner, Frank Feustel | 2011-11-01 |
| 8048726 | SOI semiconductor device with reduced topography above a substrate window area | Jens Heinrich, Sven Mueller, Kerstin Ruttloff | 2011-11-01 |
| 8040497 | Method and test structure for estimating focus settings in a lithography process based on CD measurements | Thomas Werner, Frank Feustel | 2011-10-18 |