Issued Patents All Time
Showing 51–75 of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8030209 | Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer | Thomas Werner, Frank Feustel | 2011-10-04 |
| 8017504 | Transistor having a high-k metal gate stack and a compressively stressed channel | Uwe Griebenow, Jan Hoentschel | 2011-09-13 |
| 7998823 | Method for reducing leakage currents caused by misalignment of a contact structure by increasing an error tolerance of the contact patterning process | Carsten Peters, Ralf Richter | 2011-08-16 |
| 7989352 | Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics | Frank Feustel, Thomas Werner | 2011-08-02 |
| 7977237 | Fabricating vias of different size of a semiconductor device by splitting the via patterning process | Frank Feustel, Thomas Werner | 2011-07-12 |
| 7955962 | Method of reducing contamination by providing a removable polymer protection film during microstructure processing | Ralf Richter, Frank Feustel, Thomas Werner | 2011-06-07 |
| 7932166 | Field effect transistor having a stressed contact etch stop layer with reduced conformality | Frank Feustel, Thomas Werner | 2011-04-26 |
| 7910496 | Technique for forming an interlayer dielectric material of increased reliability above a structure including closely spaced lines | Frank Feustel, Carsten Peters | 2011-03-22 |
| 7906815 | Increased reliability for a contact structure to connect an active region with a polysilicon line | Carsten Peters, Ralf Richter | 2011-03-15 |
| 7902581 | Semiconductor device comprising a contact structure based on copper and tungsten | Carsten Peters, Thomas Werner | 2011-03-08 |
| 7871941 | Method for reducing resist poisoning during patterning of stressed nitrogen-containing layers in a semiconductor device | Ralf Richter, Thomas Werner | 2011-01-18 |
| 7871877 | Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel region | Uwe Griebenow, Martin Gerhardt | 2011-01-18 |
| 7838359 | Technique for forming contact insulation layers and silicide regions with different characteristics | Christoph Schwan, Matthias Lehr | 2010-11-23 |
| 7838354 | Method for patterning contact etch stop layers by using a planarization process | Sven Mueller, Christoph Schwan | 2010-11-23 |
| 7833874 | Technique for forming an isolation trench as a stress source for strain engineering | Patrick Press, Thomas Werner | 2010-11-16 |
| 7800106 | Test structure for OPC-related shorts between lines in a semiconductor device | Frank Feustel, Thomas Werner | 2010-09-21 |
| 7763476 | Test structure for determining characteristics of semiconductor alloys in SOI transistors by x-ray diffraction | Thomas Werner, Holger Schuehrer | 2010-07-27 |
| 7763532 | Technique for forming a dielectric etch stop layer above a structure including closely spaced lines | Matthias Schaller, Roberto Klinger | 2010-07-27 |
| 7741191 | Method for preventing the formation of electrical shorts via contact ILD voids | Sven Mueller, Frank Feustel | 2010-06-22 |
| 7713815 | Semiconductor device including a vertical decoupling capacitor | Matthias Lehr, Christoph Schwan | 2010-05-11 |
| 7705352 | Test structure for estimating electromigration effects with increased robustness with respect to barrier defects in vias | Frank Feustel, Thomas Werner | 2010-04-27 |
| 7622391 | Method of forming an electrically conductive line in an integrated circuit | Thomas Werner, Ruo Qing Su | 2009-11-24 |
| 7608912 | Technique for creating different mechanical strain in different CPU regions by forming an etch stop layer having differently modified intrinsic stress | Joerg Hohage, Thomas Werner | 2009-10-27 |
| 7608501 | Technique for creating different mechanical strain by forming a contact etch stop layer stack having differently modified intrinsic stress | Carsten Peters, Matthias Schaller, Heike Salz | 2009-10-27 |
| 7563731 | Field effect transistor having a stressed dielectric layer based on an enhanced device topography | Christoph Schwan, Manfred Horstmann, Rolf Stephan | 2009-07-21 |