MG

Martin Gerhardt

Globalfoundries: 17 patents #201 of 4,424Top 5%
AM AMD: 4 patents #2,565 of 9,279Top 30%
BG Bsh Hausgeräte Gmbh: 1 patents #669 of 1,405Top 50%
Overall (All Time): #192,415 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12088101 Circuit arrangement for controlling a plurality of electrical loads Martin Pflauminger 2024-09-10
10580863 Transistor element with reduced lateral electrical field Damien Angot, Alban Zaka, Tom Herrmann, Venkata Naga Ranjith Kuma Nelluri, Jan Hoentschel +1 more 2020-03-03
10529728 Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell Ralf Richter 2020-01-07
10256134 Heat dissipative element for polysilicon resistor bank Ricardo P. Mikalo 2019-04-09
9922986 Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell and method for the formation thereof Ralf Richter 2018-03-20
9461145 OPC enlarged dummy electrode to eliminate ski slope at eSiGe Ran Yan, Jan Hoentschel 2016-10-04
9425194 Transistor devices with high-k insulation layers Stefan Flachowsky, Matthias Kessler 2016-08-23
9219013 Technique for manufacturing semiconductor devices comprising transistors with different threshold voltages Stefan Flachowsky, Matthias Kessler 2015-12-22
9136177 Methods of forming transistor devices with high-k insulation layers and the resulting devices Stefan Flachowsky, Matthias Kessler 2015-09-15
9117929 Method for forming a strained transistor by stress memorization based on a stressed implantation mask Frank Wirbeleit, Roman Boschke 2015-08-25
8614134 Shallow source and drain architecture in an active region of a semiconductor device having a pronounced surface topography by tilted implantation Peter Javorka, Juergen Faul 2013-12-24
8541885 Technique for enhancing transistor performance by transistor specific contact design Ralf Richter, Thomas Feudel, Uwe Griebenow 2013-09-24
8349694 Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy Stephan Kronholz, Markus Lenski, Andy Wei 2013-01-08
8101512 Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography Martin Trentzsch, Markus Forsberg, Manfred Horstmann 2012-01-24
7994059 Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device Ralf Richter, Martin Mazur, Joerg Hohage 2011-08-09
7964458 Method for forming a strained transistor by stress memorization based on a stressed implantation mask Frank Wirbeleit, Roman Boschke 2011-06-21
7964970 Technique for enhancing transistor performance by transistor specific contact design Ralf Richter, Thomas Feudel, Uwe Griebenow 2011-06-21
7871877 Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel region Uwe Griebenow, Kai Frohberg 2011-01-18
7659170 Method of increasing transistor drive current by recessing an isolation trench Christoph Schwan, Manfred Horstmann, Markus Forseberg 2010-02-09
7494906 Technique for transferring strain into a semiconductor region Thorsten Kammler, Frank Wirbeleit 2009-02-24
7462524 Methods for fabricating a stressed MOS device Igor Peidous, David E. Brown 2008-12-09
7348233 Methods for fabricating a CMOS device including silicide contacts Igor Peidous 2008-03-25