Issued Patents All Time
Showing 1–25 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12336230 | IC structure with MFMIS memory cell and CMOS transistor | Stefan Dünkel, Dominik Martin Kleimaier, Halid Mulaosmanovic, Johannes C. A. Muller | 2025-06-17 |
| 12159935 | Structures for a ferroelectric field-effect transistor and related methods | Halid Mulaosmanovic, Stefan Dünkel, Joachim Metzger, Robert Binder | 2024-12-03 |
| 12027226 | Structure including a cross-bar router and method | Venkatesh P. Gopinath, Navneet Jain | 2024-07-02 |
| 10319732 | Transistor element including a buried insulating layer having enhanced functionality | Ralf Richter, Jochen Willi. Poth, Stefan Duenkel, Sandhya Chandrashekhar, Zhi-Yuan Wu | 2019-06-11 |
| 10283490 | Communicating optical signals between stacked dies | Jan Hoentschel, Alexander Ebermann | 2019-05-07 |
| 10249633 | Flash memory device | Ralf Richter, Jan Paul | 2019-04-02 |
| 10163933 | Ferro-FET device with buried buffer/ferroelectric layer stack | Ralf Richter, Stefan Dünkel, Martin Trentzsch | 2018-12-25 |
| 10157996 | Methods for forming integrated circuits that include a dummy gate structure | Elliot John Smith, Jan Hoentschel, Nigel Chan | 2018-12-18 |
| 10084057 | NVM device in SOI technology and method of fabricating an according device | Martin Trentzsch, Stefan Flachowsky, Axel Henke | 2018-09-25 |
| 10033383 | Programmable logic elements and methods of operating the same | Ralf Richter, Stefan Duenkel | 2018-07-24 |
| 9871050 | Flash memory device | Ralf Richter, Jan Paul | 2018-01-16 |
| 9806067 | Die-die stacking | Jan Hoentschel, Alexander Ebermann | 2017-10-31 |
| 9793372 | Integrated circuit including a dummy gate structure and method for the formation thereof | Elliot John Smith, Jan Hoentschel, Nigel Chan | 2017-10-17 |
| 9754951 | Semiconductor device with a memory device and a high-K metal gate transistor | Ralf Richter | 2017-09-05 |
| 9711513 | Semiconductor structure including a nonvolatile memory cell and method for the formation thereof | Alban Zaka, Tom Herrmann, El Mehdi Bazizi | 2017-07-18 |
| 9698179 | Capacitor structure and method of forming a capacitor structure | Elliot John Smith, Jan Hoentschel, Alexander Ebermann | 2017-07-04 |
| 9608112 | BULEX contacts in advanced FDSOI techniques | Elliot John Smith, Tom Hasche, Jan Hoentschel | 2017-03-28 |
| 9590118 | Wafer with SOI structure having a buried insulating multilayer structure and semiconductor device structure | Elliot John Smith, Nigel Chan, Jan Hoentschel | 2017-03-07 |
| 9583640 | Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure | Ralf Richter, Carsten Grass, Tom Herrmann | 2017-02-28 |
| 9548312 | Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure including a nonvolatile memory cell | Alexander Ebermann, Martin Schulze | 2017-01-17 |
| 9490189 | Semiconductor device comprising a stacked die configuration including an integrated peltier element | Uwe Griebenow, Jan Hoentschel, Thilo Scheiper | 2016-11-08 |
| 9281200 | Enhanced patterning uniformity of gate electrodes of a semiconductor device by late gate doping | Hans-Juergen Thees, Martin Mazur, Steffen Laufer | 2016-03-08 |
| 9184095 | Contact bars with reduced fringing capacitance in a semiconductor device | Thilo Scheiper, Uwe Griebenow, Jan Hoentschel, Andy Wei | 2015-11-10 |
| 9123825 | Methods for fabricating FinFET integrated circuits using laser interference lithography techniques | Alexander Ebermann, Carsten Grass, Jan Hoentschel | 2015-09-01 |
| 9123827 | Methods for fabricating integrated circuits with fully silicided gate electrode structures | Jan Hoentschel, Alexander Ebermann, Carsten Grass | 2015-09-01 |