Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12046603 | Semiconductor structure including sectioned well region | Navneet Jain, Mahbub Rashed | 2024-07-23 |
| 11488967 | Eight-transistor static random access memory cell | Jorg Schmid | 2022-11-01 |
| 11127860 | Extended-drain field-effect transistors including a floating gate | Ming-Cheng Chang | 2021-09-21 |
| 10923482 | IC product with a novel bit cell design and a memory array comprising such bit cells | Germain Bossu | 2021-02-16 |
| 10909298 | Well contact cell with doped tap region separated from active region, and methods to form same | Navneet Jain | 2021-02-02 |
| 10811433 | High-voltage transistor device with thick gate insulation layers | Elliot John Smith, Nilesh Kenkare | 2020-10-20 |
| 10593674 | Deep fence isolation for logic cells | Ming-Cheng Chang, Elliot John Smith | 2020-03-17 |
| 10559490 | Dual-depth STI cavity extension and method of production thereof | Elliot John Smith, Ming-Cheng Chang | 2020-02-11 |
| 10504906 | FinFET SRAM layout and method of making the same | Ming-Cheng Chang, Ralf van Bentum | 2019-12-10 |
| 10418380 | High-voltage transistor device with thick gate insulation layers | Elliot John Smith, Nilesh Kenkare | 2019-09-17 |
| 10396084 | Semiconductor devices including self-aligned active regions for planar transistor architecture | Elliot John Smith, Nilesh Kenkare, Hongsik Yoon | 2019-08-27 |
| 10319827 | High voltage transistor using buried insulating layer as gate dielectric | Elliot John Smith | 2019-06-11 |
| 10311201 | Alignment key design rule check for correct placement of abutting cells in an integrated circuit | Germain Bossu | 2019-06-04 |
| 10177163 | SOI-based floating gate memory cell | Elliot John Smith | 2019-01-08 |
| 10157996 | Methods for forming integrated circuits that include a dummy gate structure | Elliot John Smith, Jan Hoentschel, Sven Beyer | 2018-12-18 |
| 10079605 | Semiconductor structure with back-gate switching | Michael Otto | 2018-09-18 |
| 9847347 | Semiconductor structure including a first transistor at a semiconductor-on-insulator region and a second transistor at a bulk region and method for the formation thereof | Elliot John Smith, Nilesh Kenkare | 2017-12-19 |
| 9793372 | Integrated circuit including a dummy gate structure and method for the formation thereof | Elliot John Smith, Jan Hoentschel, Sven Beyer | 2017-10-17 |
| 9768084 | Inline monitoring of transistor-to-transistor critical dimension | Elliot John Smith | 2017-09-19 |
| 9762245 | Semiconductor structure with back-gate switching | Michael Otto | 2017-09-12 |
| 9685336 | Process monitoring for gate cut mask | Elliot John Smith | 2017-06-20 |
| 9590118 | Wafer with SOI structure having a buried insulating multilayer structure and semiconductor device structure | Elliot John Smith, Sven Beyer, Jan Hoentschel | 2017-03-07 |
| 9490007 | Device comprising a plurality of FDSOI static random-access memory bitcells and method of operation thereof | Germain Bossu, Michael Otto | 2016-11-08 |
| 8953388 | Memory cell assembly including an avoid disturb cell | Michael Otto | 2015-02-10 |
| 8921898 | Device including an array of memory cells and well contact areas, and method for the formation thereof | Michael Otto | 2014-12-30 |