Issued Patents All Time
Showing 51–75 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8445344 | Uniform high-k metal gate stacks by adjusting threshold voltage for sophisticated transistors by diffusing a metal species prior to gate patterning | Richard J. Carter, Falk Graetsch, Martin Trentzsch, Berthold Reimer, Robert Binder +1 more | 2013-05-21 |
| 8409942 | Replacement gate approach based on a reverse offset spacer applied prior to work function metal deposition | Thilo Scheiper, Uwe Griebenow, Jan Hoentschel | 2013-04-02 |
| 8404550 | Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement | Thilo Scheiper, Andy Wei, Jan Hoentschel | 2013-03-26 |
| 8378432 | Maintaining integrity of a high-K gate stack by an offset spacer used to determine an offset of a strain-inducing semiconductor alloy | Richard J. Carter, Martin Trentzsch | 2013-02-19 |
| 8367495 | Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric material | Markus Lenski, Richard J. Carter, Klaus Hempel | 2013-02-05 |
| 8359561 | Equivalence verification between transaction level models and RTL at the example to processors | Joerg Bormann, Sebastian Skalberg | 2013-01-22 |
| 8357604 | Work function adjustment in high-k gate stacks for devices of different threshold voltage | Jan Hoentschel, Thilo Scheiper | 2013-01-22 |
| 8343837 | Work function adjustment in a high-k gate electrode structure after transistor fabrication by using lanthanum | Richard J. Carter, Joachim Metzger, Robert Binder | 2013-01-01 |
| 8338894 | Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etch | Uwe Griebenow, Jan Hoentschel | 2012-12-25 |
| 8329549 | Enhancing integrity of a high-k gate stack by protecting a liner at the gate bottom during gate head exposure | Frank Seliger, Gunter Grasshoff | 2012-12-11 |
| 8329531 | Strain memorization in strained SOI substrates of semiconductor devices | Jan Hoentschel, Uwe Griebenow, Thilo Scheiper | 2012-12-11 |
| 8318564 | Performance enhancement in transistors comprising high-k metal gate stack by an early extension implantation | Thilo Scheiper, Jan Hoentschel, Uwe Griebenow | 2012-11-27 |
| 8318598 | Contacts and vias of a semiconductor device formed by a hard mask and double exposure | Kai Frohberg, Katrin Reiche, Kerstin Ruttloff | 2012-11-27 |
| 8293610 | Semiconductor device comprising a metal gate stack of reduced height and method of forming the same | Rolf Stephan, Martin Trentzsch, Patrick Press | 2012-10-23 |
| 8283232 | Enhanced etch stop capability during patterning of silicon nitride including layer stacks by providing a chemically formed oxide layer during semiconductor processing | Berthold Reimer, Falk Graetsch | 2012-10-09 |
| 8247275 | Strain engineering in three-dimensional transistors based on globally strained semiconductor base layers | Jan Hoentschel, Uwe Griebenow | 2012-08-21 |
| 8241977 | Short channel transistor with reduced length variation by using amorphous electrode material during implantation | Thilo Scheiper, Andy Wei | 2012-08-14 |
| 8232188 | High-K metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning | Klaus Hempel, Thilo Scheiper, Stefanie Steiner | 2012-07-31 |
| 8198192 | Adjusting threshold voltage for sophisticated transistors by diffusing a gate dielectric cap layer material prior to gate dielectric stabilization | Richard J. Carter, Martin Trentzsch, Rohit Pal | 2012-06-12 |
| 8198152 | Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials | Jan Hoentschel, Thilo Scheiper, Uwe Griebenow | 2012-06-12 |
| 8143132 | Transistor including a high-K metal gate electrode structure formed on the basis of a simplified spacer regime | Jan Hoentschel, Thilo Scheiper | 2012-03-27 |
| 8138571 | Semiconductor device comprising isolation trenches inducing different types of strain | Christoph Schwan, Joe Bloomquist, Peter Javorka, Manfred Horstmann, Markus Forsberg +2 more | 2012-03-20 |
| 8048792 | Superior fill conditions in a replacement gate approach by corner rounding prior to completely removing a placeholder material | Klaus Hempel, Andreas Ott, Stephan Kruegel | 2011-11-01 |
| 8039335 | Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain | Manfred Horstmann, Patrick Press, Wolfgang Buchholtz | 2011-10-18 |
| 8030148 | Structured strained substrate for forming strained transistors with reduced thickness of active layer | Jan Hoentschel, Andy Wei | 2011-10-04 |