Issued Patents All Time
Showing 25 most recent of 152 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7544999 | SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate | Andy Wei, Mark B. Fuselier | 2009-06-09 |
| 7432136 | Transistors with controllable threshold voltages, and various methods of making and operating same | Mark B. Fuselier, Andy Wei | 2008-10-07 |
| 7417250 | Strained-silicon device with different silicon thicknesses | James F. Buller, Qi Xiang, Bin Yu | 2008-08-26 |
| 7335568 | Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same | Andy Wei, Mark B. Fuselier | 2008-02-26 |
| 7253045 | Selective P-channel VT adjustment in SiGe system for leakage optimization | David Wu, Hormuzdiar E. Nariman | 2007-08-07 |
| 7208383 | Method of manufacturing a semiconductor component | Chad Weintraub, James F. Buller, Jon D. Cheek | 2007-04-24 |
| 7180136 | Biased, triple-well fully depleted SOI structure | Andy Wei, Mark B. Fuselier | 2007-02-20 |
| 7129142 | Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same | Andy Wei, Mark B. Fuselier | 2006-10-31 |
| 6979878 | Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites | Mark I. Gardner, H. Jim Fulford | 2005-12-27 |
| 6949436 | Composite spacer liner for improved transistor performance | James F. Buller, David Wu, Scott Luning, Daniel Kadosh | 2005-09-27 |
| 6936506 | Strained-silicon devices with different silicon thicknesses | James F. Buller, Qi Xiang, Bin Yu | 2005-08-30 |
| 6919236 | Biased, triple-well fully depleted SOI structure, and various methods of making and operating same | Andy Wei, Mark B. Fuselier | 2005-07-19 |
| 6884702 | Method of making an SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate | Andy Wei, Mark B. Fuselier | 2005-04-26 |
| 6876037 | Fully-depleted SOI device | Andy Wei, Mark B. Fuselier | 2005-04-05 |
| 6833307 | Method for manufacturing a semiconductor component having an early halo implant | Chad Weintraub, James F. Buller, Jon D. Cheek | 2004-12-21 |
| 6822260 | Linewidth measurement structure with embedded scatterometry structure | Hormuzdiar E. Nariman | 2004-11-23 |
| 6812506 | Polysilicon linewidth measurement structure with embedded transistor | Hormuzdiar E. Nariman | 2004-11-02 |
| 6801096 | Ring oscillator with embedded scatterometry grate array | Hormuzdiar E. Nariman, James F. Buller | 2004-10-05 |
| 6780686 | Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions | Andy Wei, Mark B. Fuselier | 2004-08-24 |
| 6764908 | Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized NMOS and PMOS drive currents | Daniel Kadosh, Qi Xiang, Bin Yu | 2004-07-20 |
| 6737332 | Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same | Mark B. Fuselier, Andy Wei | 2004-05-18 |
| 6727534 | Electrically programmed MOS transistor source/drain series resistance | James F. Buller, Qi Xiang | 2004-04-27 |
| 6727136 | Formation of ultra-shallow depth source/drain extensions for MOS transistors | James F. Buller, David Wu, Akif Sultan | 2004-04-27 |
| 6707106 | Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer | Qi Xiang, James F. Buller | 2004-03-16 |
| 6689671 | Low temperature solid-phase epitaxy fabrication process for MOS devices built on strained semiconductor substrate | Bin Yu | 2004-02-10 |