Issued Patents All Time
Showing 26–50 of 152 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6674135 | Semiconductor structure having elevated salicided source/drain regions and metal gate electrode on nitride/oxide dielectric | Jon D. Cheek, Mark I. Gardner | 2004-01-06 |
| 6661057 | Tri-level segmented control transistor and fabrication method | Robert Dawson, Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Mark W. Michael +1 more | 2003-12-09 |
| 6638829 | Semiconductor structure having a metal gate electrode and elevated salicided source/drain regions and a method for manufacture | Jon D. Cheek, Mark I. Gardner | 2003-10-28 |
| 6589847 | Tilted counter-doped implant to sharpen halo profile | Daniel Kadosh, Scott Luning | 2003-07-08 |
| 6580122 | Transistor device having an enhanced width dimension and a method of making same | Jon D. Cheek, John G. Pellerin | 2003-06-17 |
| 6566696 | Self-aligned VT implant | Jon D. Cheek, Mark W. Michael, James F. Buller | 2003-05-20 |
| 6552776 | Photolithographic system including light filter that compensates for lens error | Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more | 2003-04-22 |
| 6433400 | Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolation structure | Mark I. Gardner, H. Jim Fulford | 2002-08-13 |
| 6417539 | High density memory cell assembly and methods | Mark I. Gardner, Jon D. Cheek | 2002-07-09 |
| 6410409 | Implanted barrier layer for retarding upward diffusion of substrate dopant | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 2002-06-25 |
| 6406964 | Method of controlling junction recesses in a semiconductor device | Jon D. Cheek, John G. Pellerin | 2002-06-18 |
| 6380055 | Dopant diffusion-retarding barrier region formed within polysilicon gate layer | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 2002-04-30 |
| 6372588 | Method of making an IGFET using solid phase diffusion to dope the gate, source and drain | Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more | 2002-04-16 |
| 6372587 | Angled halo implant tailoring using implant mask | Jon D. Cheek, Scott Luning | 2002-04-16 |
| 6346426 | Method and apparatus for characterizing semiconductor device performance variations based on independent critical dimension measurements | Anthony J. Toprac, Jon D. Cheek | 2002-02-12 |
| 6323519 | Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process | Mark I. Gardner, Charles E. May | 2001-11-27 |
| 6316302 | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant | Jon D. Cheek, Anthony J. Toprac | 2001-11-13 |
| 6300205 | Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo regions | H. Jim Fulford, Jon D. Cheek, James F. Buller | 2001-10-09 |
| 6274415 | Self-aligned Vt implant | Jon D. Cheek, Mark W. Michael, James F. Buller | 2001-08-14 |
| 6261936 | Poly gate CD passivation for metrology control | Marilyn I. Wright, Jon D. Cheek | 2001-07-17 |
| 6258680 | Integrated circuit gate conductor which uses layered spacers to produce a graded junction | H. Jim Fulford, Mark I. Gardner | 2001-07-10 |
| 6258646 | CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof | H. Jim Fulford, Mark I. Gardner | 2001-07-10 |
| 6259142 | Multiple split gate semiconductor device and fabrication method | Robert Dawson, Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Mark W. Michael +1 more | 2001-07-10 |
| 6245689 | Process for reliable ultrathin oxynitride formation | Ming-Yin Hao, Robert B. Ogle | 2001-06-12 |
| 6245649 | Method for forming a retrograde impurity profile | James F. Buller, Jon D. Cheek, Daniel Kadosh, H. Jim Fulford | 2001-06-12 |