DW

Derick J. Wristers

AM AMD: 151 patents #11 of 9,279Top 1%
🗺 Texas: #176 of 125,132 inventorsTop 1%
Overall (All Time): #6,064 of 4,157,543Top 1%
152
Patents All Time

Issued Patents All Time

Showing 76–100 of 152 patents

Patent #TitleCo-InventorsDate
6100148 Semiconductor device having a liner defining the depth of an active region, and fabrication thereof Mark I. Gardner, Jim Fulford 2000-08-08
6100146 Method of forming trench transistor with insulative spacers Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more 2000-08-08
6096591 Method of making an IGFET and a protected resistor with reduced processing steps Mark I. Gardner, Daniel Kadosh 2000-08-01
6096615 Method of forming a semiconductor device having narrow gate electrode Mark I. Gardner 2000-08-01
6096639 Method of forming a local interconnect by conductive layer patterning Robert Dawson, Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Mark W. Michael +1 more 2000-08-01
6097062 Optimized trench edge formation integrated with high quality gate formation Mark I. Gardner, H. Jim Fulford 2000-08-01
6093611 Oxide liner for high reliability with reduced encroachment of the source/drain region Mark I. Gardner, H. Jim Fulford 2000-07-25
6087706 Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls Robert Dawson, Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Mark W. Michael +1 more 2000-07-11
6083272 Method of adjusting currents on a semiconductor device having transistors of varying density John L. Nistler 2000-07-04
6080629 Ion implantation into a gate electrode layer using an implant profile displacement layer Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more 2000-06-27
6074906 Complementary metal-oxide semiconductor device having source/drain regions formed using multiple spacers Jon D. Cheek, H. Jim Fulford 2000-06-13
6060345 Method of making NMOS and PMOS devices with reduced masking steps Frederick N. Hause, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Mark W. Michael +1 more 2000-05-09
6060369 Nitrogen bearing sacrificial oxide with subsequent high nitrogen dopant profile for high performance MOSFET Mark I. Gardner, H. Jim Fulford 2000-05-09
6057194 Method of forming trench transistor in combination with trench array H. Jim Fulford, Mark I. Gardner 2000-05-02
6051459 Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate Mark I. Gardner, Daniel Kadosh, Frederick N. Hause 2000-04-18
6051865 Transistor having a barrier layer below a high permittivity gate dielectric Mark I. Gardner, Mark C. Gilmer 2000-04-18
6051471 Method for making asymmetrical N-channel and symmetrical P-channel devices Mark I. Gardner, H. Jim Fulford 2000-04-18
6048785 Semiconductor fabrication method of combining a plurality of fields defined by a reticle image using segment stitching H. Jim Fulford, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more 2000-04-11
6040607 Self aligned method for differential oxidation rate at shallow trench isolation edge H. Jim Fulford, Mark I. Gardner 2000-03-21
6030752 Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device H. Jim Fulford, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more 2000-02-29
6018180 Transistor formation with LI overetch immunity Jon D. Cheek, H. Jim Fulford 2000-01-25
6018179 Transistors having a scaled channel length and integrated spacers with enhanced silicidation properties Mark I. Gardner, Fred N. Hause 2000-01-25
5994175 High performance MOSFET with low resistance design Mark I. Gardner, H. Jim Fulford 1999-11-30
5994193 Method of making high performance MOSFET with integrated poly/metal gate electrode Mark I. Gardner, Jon D. Cheek 1999-11-30
5981365 Stacked poly-oxide-poly gate for improved silicide formation Jon D. Cheek, Mark I. Gardner 1999-11-09