Issued Patents All Time
Showing 51–75 of 152 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6242330 | Process for breaking silicide stringers extending between silicide areas of different active regions | Jon D. Cheek, Fred N. Hause | 2001-06-05 |
| 6225188 | Self aligned method for differential oxidation rate at shallow trench isolation edge | H. Jim Fulford, Mark I. Gardner | 2001-05-01 |
| 6225151 | Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Daniel Kadosh +2 more | 2001-05-01 |
| 6204148 | Method of making a semiconductor device having a grown polysilicon layer | Mark I. Gardner, H. Jim Fulford | 2001-03-20 |
| 6201278 | Trench transistor with insulative spacers | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 2001-03-13 |
| 6197645 | Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls | Mark W. Michael, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause +1 more | 2001-03-06 |
| 6188114 | Method of forming an insulated-gate field-effect transistor with metal spacers | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 2001-02-13 |
| 6188107 | High performance transistor fabricated on a dielectric film and method of making same | Mark I. Gardner, Frederick N. Hause | 2001-02-13 |
| 6187620 | Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions | H. Jim Fulford, Mark I. Gardner | 2001-02-13 |
| 6180475 | Transistor formation with local interconnect overetch immunity | Jon D. Cheek, H. Jim Fulford | 2001-01-30 |
| 6166354 | System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication | Frederick N. Hause, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Mark W. Michael +1 more | 2000-12-26 |
| 6162694 | Method of forming a metal gate electrode using replaced polysilicon structure | Jon D. Cheek, Mark I. Gardner | 2000-12-19 |
| 6162688 | Method of fabricating a transistor with a dielectric underlayer and device incorporating same | Mark I. Gardner, H. Jim Fulford | 2000-12-19 |
| 6160300 | Multi-layer gate conductor having a diffusion barrier in the bottom layer | Mark I. Gardner, Charles E. May | 2000-12-12 |
| 6159812 | Reduced boron diffusion by use of a pre-anneal | Jon D. Cheek, William A. Whigham | 2000-12-12 |
| 6150695 | Multilevel transistor formation employing a local substrate formed within a shallow trench | Mark I. Gardner, Daniel Kadosh | 2000-11-21 |
| 6146978 | Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance | Mark W. Michael, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause +1 more | 2000-11-14 |
| 6124610 | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant | Jon D. Cheek, Anthony J. Toprac | 2000-09-26 |
| 6118163 | Transistor with integrated poly/metal gate electrode | Mark I. Gardner, Jon D. Cheek | 2000-09-12 |
| 6114211 | Semiconductor device with vertical halo region and methods of manufacture | H. Jim Fulford, Jon D. Cheek, James F. Buller | 2000-09-05 |
| 6111260 | Method and apparatus for in situ anneal during ion implant | Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more | 2000-08-29 |
| 6107130 | CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions | H. Jim Fulford, Mark I. Gardner | 2000-08-22 |
| 6104063 | Multiple spacer formation/removal technique for forming a graded junction | H. Jim Fulford, Mark I. Gardner | 2000-08-15 |
| 6104077 | Semiconductor device having gate electrode with a sidewall air gap | Mark I. Gardner, Jon D. Cheek | 2000-08-15 |
| 6103559 | Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication | Mark I. Gardner, H. Jim Fulford | 2000-08-15 |