DW

Derick J. Wristers

AM AMD: 151 patents #11 of 9,279Top 1%
🗺 Texas: #176 of 125,132 inventorsTop 1%
Overall (All Time): #6,064 of 4,157,543Top 1%
152
Patents All Time

Issued Patents All Time

Showing 101–125 of 152 patents

Patent #TitleCo-InventorsDate
5977600 Formation of shortage protection region Jon D. Cheek, H. James Fulford 1999-11-02
5976956 Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more 1999-11-02
5976925 Process of fabricating a semiconductor devise having asymmetrically-doped active region and gate electrode Jon Cheek, James F. Buller 1999-11-02
5976924 Method of making a self-aligned disposable gate electrode for advanced CMOS design Mark I. Gardner, H. Jim Fulford 1999-11-02
5970311 Method and structure for optimizing the performance of a semiconductor device having dense transistors Jon Cheek, Daniel Kadosh 1999-10-19
5969407 MOSFET device with an amorphized source Mark I. Gardner, H. Jim Fulford 1999-10-19
5962894 Trench transistor with metal spacers Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more 1999-10-05
5959333 Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor Mark I. Gardner, H. Jim Fulford 1999-09-28
5950091 Method of making a polysilicon gate conductor of an integrated circuit formed as a sidewall spacer on a sacrificial material H. Jim Fulford, Mark I. Gardner 1999-09-07
5943550 Method of processing a semiconductor wafer for controlling drive current H. Jim Fulford 1999-08-24
5939763 Ultrathin oxynitride structure and process for VLSI applications Ming-Yin Hao, Robert B. Ogle 1999-08-17
5935766 Method of forming a conductive plug in an interlevel dielectric Jon D. Cheek, Daniel Kadosh 1999-08-10
5937299 Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls Mark W. Michael, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause +1 more 1999-08-10
5930634 Method of making an IGFET with a multilevel gate Frederick N. Hause, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Mark W. Michael +1 more 1999-07-27
5930642 Transistor with buried insulative layer beneath the channel region Bradley T. Moore, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause +1 more 1999-07-27
5923983 Integrated circuit gate conductor having a gate dielectric which is substantially resistant to hot carrier effects H. Jim Fulford, Mark I. Gardner 1999-07-13
5918126 Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size H. Jim Fulford, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more 1999-06-29
5918129 Method of channel doping using diffusion from implanted polysilicon H. Jim Fulford, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more 1999-06-29
5899732 Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more 1999-05-04
5891787 Semiconductor fabrication employing implantation of excess atoms at the edges of a trench isolation structure Mark I. Gardner, H. Jim Fulford 1999-04-06
5888675 Reticle that compensates for radiation-induced lens error in a photolithographic system Bradley T. Moore, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause +1 more 1999-03-30
5885887 Method of making an igfet with selectively doped multilevel polysilicon gate Frederick N. Hause, Robert Dawson, H. Jim Fulford Jr., Mark I. Gardner, Mark W. Michael +1 more 1999-03-23
5885877 Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Daniel Kadosh +2 more 1999-03-23
5877058 Method of forming an insulated-gate field-effect transistor with metal spacers Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more 1999-03-02
5877050 Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals Mark I. Gardner, H. Jim Fulford 1999-03-02